2013-08-02 16:46:45 +02:00
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/*
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2018-01-09 08:38:22 +01:00
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* Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2018 SAP SE. All rights reserved.
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2013-08-02 16:46:45 +02:00
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#include "precompiled.hpp"
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#include "runtime/icache.hpp"
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// Use inline assembler to implement icache flush.
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2013-12-11 00:06:11 +01:00
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int ICache::ppc64_flush_icache(address start, int lines, int magic) {
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2013-08-02 16:46:45 +02:00
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address end = start + (unsigned int)lines*ICache::line_size;
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assert(start <= end, "flush_icache parms");
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2018-01-09 08:38:22 +01:00
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// Store modified cache lines from data cache.
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2013-12-11 00:06:11 +01:00
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for (address a = start; a < end; a += ICache::line_size) {
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2013-08-02 16:46:45 +02:00
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__asm__ __volatile__(
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2013-12-11 00:06:11 +01:00
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"dcbst 0, %0 \n"
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:
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: "r" (a)
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: "memory");
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2013-08-02 16:46:45 +02:00
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}
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// sync instruction
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__asm__ __volatile__(
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"sync \n"
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:
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:
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: "memory");
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2018-01-09 08:38:22 +01:00
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// Invalidate respective cache lines in instruction cache.
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2013-12-11 00:06:11 +01:00
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for (address a = start; a < end; a += ICache::line_size) {
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2013-08-02 16:46:45 +02:00
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__asm__ __volatile__(
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2013-12-11 00:06:11 +01:00
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"icbi 0, %0 \n"
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:
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: "r" (a)
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: "memory");
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2013-08-02 16:46:45 +02:00
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}
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2018-01-09 08:38:22 +01:00
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// Discard fetched instructions.
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2013-08-02 16:46:45 +02:00
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__asm__ __volatile__(
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2013-12-11 00:06:11 +01:00
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"isync \n"
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:
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:
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: "memory");
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2013-08-02 16:46:45 +02:00
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return magic;
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}
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void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) {
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2013-12-11 00:06:11 +01:00
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*flush_icache_stub = (ICache::flush_icache_stub_t)ICache::ppc64_flush_icache;
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2013-08-02 16:46:45 +02:00
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2018-01-09 08:38:22 +01:00
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// First call to flush itself.
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// Pointless since we call C, but it is expected to get
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// executed during VM_Version::determine_features().
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2013-08-02 16:46:45 +02:00
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ICache::invalidate_range((address)(*flush_icache_stub), 0);
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}
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