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8290917: x86: Memory-operand arithmetic instructions have too low costs

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Reviewed-by: kvn, sviswanathan, jbhateja
This commit is contained in:
Quan Anh Mai 2022-09-16 20:07:59 +00:00 committed by Sandhya Viswanathan
parent 4b8399b5f0
commit 01e7b88199
4 changed files with 165 additions and 316 deletions
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10
src/hotspot/cpu/x86/x86_32.ad
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@ -7137,7 +7137,7 @@ instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (AddI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
ins_cost(150);
format %{ "ADD $dst,$src" %}
opcode(0x03);
ins_encode( OpcP, RegMem( dst, src) );
@ -7506,7 +7506,7 @@ instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (SubI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
ins_cost(150);
format %{ "SUB $dst,$src" %}
opcode(0x2B);
ins_encode( OpcP, RegMem( dst, src) );
@ -8179,7 +8179,7 @@ instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (AndI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
ins_cost(150);
format %{ "AND $dst,$src" %}
opcode(0x23);
ins_encode( OpcP, RegMem( dst, src) );
@ -8370,7 +8370,7 @@ instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (OrI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
ins_cost(150);
format %{ "OR $dst,$src" %}
opcode(0x0B);
ins_encode( OpcP, RegMem( dst, src) );
@ -8577,7 +8577,7 @@ instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (XorI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
ins_cost(150);
format %{ "XOR $dst,$src" %}
opcode(0x33);
ins_encode( OpcP, RegMem(dst, src) );

340
src/hotspot/cpu/x86/x86_64.ad
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@ -3678,17 +3678,6 @@ operand no_rax_rdx_RegL()
interface(REG_INTER);
%}
operand no_rax_RegL()
%{
constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
match(RegL);
match(rRegL);
match(rdx_RegL);
format %{ %}
interface(REG_INTER);
%}
operand rax_RegL()
%{
constraint(ALLOC_IN_RC(long_rax_reg));
@ -7667,7 +7656,7 @@ instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
match(Set dst (AddI dst (LoadI src)));
effect(KILL cr);
ins_cost(125); // XXX
ins_cost(150); // XXX
format %{ "addl $dst, $src\t# int" %}
ins_encode %{
__ addl($dst$$Register, $src$$Address);
@ -7837,7 +7826,7 @@ instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
match(Set dst (AddL dst (LoadL src)));
effect(KILL cr);
ins_cost(125); // XXX
ins_cost(150); // XXX
format %{ "addq $dst, $src\t# long" %}
ins_encode %{
__ addq($dst$$Register, $src$$Address);
@ -8513,24 +8502,12 @@ instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
ins_pipe(ialu_reg_reg);
%}
instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
%{
match(Set dst (SubI dst src));
effect(KILL cr);
format %{ "subl $dst, $src\t# int" %}
ins_encode %{
__ subl($dst$$Register, $src$$constant);
%}
ins_pipe(ialu_reg);
%}
instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
%{
match(Set dst (SubI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
ins_cost(150);
format %{ "subl $dst, $src\t# int" %}
ins_encode %{
__ subl($dst$$Register, $src$$Address);
@ -8551,19 +8528,6 @@ instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
ins_pipe(ialu_mem_reg);
%}
instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
%{
match(Set dst (StoreI dst (SubI (LoadI dst) src)));
effect(KILL cr);
ins_cost(125); // XXX
format %{ "subl $dst, $src\t# int" %}
ins_encode %{
__ subl($dst$$Address, $src$$constant);
%}
ins_pipe(ialu_mem_imm);
%}
instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
%{
match(Set dst (SubL dst src));
@ -8576,24 +8540,12 @@ instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
ins_pipe(ialu_reg_reg);
%}
instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
%{
match(Set dst (SubL dst src));
effect(KILL cr);
format %{ "subq $dst, $src\t# long" %}
ins_encode %{
__ subq($dst$$Register, $src$$constant);
%}
ins_pipe(ialu_reg);
%}
instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
%{
match(Set dst (SubL dst (LoadL src)));
effect(KILL cr);
ins_cost(125);
ins_cost(150);
format %{ "subq $dst, $src\t# long" %}
ins_encode %{
__ subq($dst$$Register, $src$$Address);
@ -8614,19 +8566,6 @@ instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
ins_pipe(ialu_mem_reg);
%}
instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
%{
match(Set dst (StoreL dst (SubL (LoadL dst) src)));
effect(KILL cr);
ins_cost(125); // XXX
format %{ "subq $dst, $src\t# long" %}
ins_encode %{
__ subq($dst$$Address, $src$$constant);
%}
ins_pipe(ialu_mem_imm);
%}
// Subtract from a pointer
// XXX hmpf???
instruct subP_rReg(rRegP dst, rRegI src, immI_0 zero, rFlagsReg cr)
@ -8830,7 +8769,7 @@ instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
ins_pipe(ialu_reg_mem_alu0);
%}
instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
instruct mulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr)
%{
match(Set dst (MulHiL src rax));
effect(USE_KILL rax, KILL cr);
@ -8843,7 +8782,7 @@ instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
ins_pipe(ialu_reg_reg_alu0);
%}
instruct umulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
instruct umulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr)
%{
match(Set dst (UMulHiL src rax));
effect(USE_KILL rax, KILL cr);
@ -8996,71 +8935,6 @@ instruct udivModL_rReg_divmod(rax_RegL rax, no_rax_rdx_RegL tmp, rdx_RegL rdx,
ins_pipe(pipe_slow);
%}
//----------- DivL-By-Constant-Expansions--------------------------------------
// DivI cases are handled by the compiler
// Magic constant, reciprocal of 10
instruct loadConL_0x6666666666666667(rRegL dst)
%{
effect(DEF dst);
format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
ins_encode(load_immL(dst, 0x6666666666666667));
ins_pipe(ialu_reg);
%}
instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
%{
effect(DEF dst, USE src, USE_KILL rax, KILL cr);
format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
ins_encode %{
__ imulq($src$$Register);
%}
ins_pipe(ialu_reg_reg_alu0);
%}
instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
%{
effect(USE_DEF dst, KILL cr);
format %{ "sarq $dst, #63\t# Used in div-by-10" %}
ins_encode %{
__ sarq($dst$$Register, 63);
%}
ins_pipe(ialu_reg);
%}
instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
%{
effect(USE_DEF dst, KILL cr);
format %{ "sarq $dst, #2\t# Used in div-by-10" %}
ins_encode %{
__ sarq($dst$$Register, 2);
%}
ins_pipe(ialu_reg);
%}
instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
%{
match(Set dst (DivL src div));
ins_cost((5+8)*100);
expand %{
rax_RegL rax; // Killed temp
rFlagsReg cr; // Killed
loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
sarL_rReg_63(src, cr); // sarq src, 63
sarL_rReg_2(dst, cr); // sarq rdx, 2
subL_rReg(dst, src, cr); // subl rdx, src
%}
%}
//-----------------------------------------------------------------------------
instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
rFlagsReg cr)
%{
@ -9127,32 +9001,6 @@ instruct umodL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, rFlagsReg c
%}
// Integer Shift Instructions
// Shift Left by one
instruct salI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (LShiftI dst shift));
effect(KILL cr);
format %{ "sall $dst, $shift" %}
ins_encode %{
__ sall($dst$$Register, $shift$$constant);
%}
ins_pipe(ialu_reg);
%}
// Shift Left by one
instruct salI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
effect(KILL cr);
format %{ "sall $dst, $shift\t" %}
ins_encode %{
__ sall($dst$$Address, $shift$$constant);
%}
ins_pipe(ialu_mem_imm);
%}
// Shift Left by 8-bit immediate
instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
%{
@ -9231,32 +9079,6 @@ instruct salI_mem_rReg(rRegI dst, memory src, rRegI shift)
ins_pipe(ialu_reg_mem);
%}
// Arithmetic shift right by one
instruct sarI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (RShiftI dst shift));
effect(KILL cr);
format %{ "sarl $dst, $shift" %}
ins_encode %{
__ sarl($dst$$Register, $shift$$constant);
%}
ins_pipe(ialu_reg);
%}
// Arithmetic shift right by one
instruct sarI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
effect(KILL cr);
format %{ "sarl $dst, $shift" %}
ins_encode %{
__ sarl($dst$$Address, $shift$$constant);
%}
ins_pipe(ialu_mem_imm);
%}
// Arithmetic Shift Right by 8-bit immediate
instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
%{
@ -9334,32 +9156,6 @@ instruct sarI_mem_rReg(rRegI dst, memory src, rRegI shift)
ins_pipe(ialu_reg_mem);
%}
// Logical shift right by one
instruct shrI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (URShiftI dst shift));
effect(KILL cr);
format %{ "shrl $dst, $shift" %}
ins_encode %{
__ shrl($dst$$Register, $shift$$constant);
%}
ins_pipe(ialu_reg);
%}
// Logical shift right by one
instruct shrI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
effect(KILL cr);
format %{ "shrl $dst, $shift" %}
ins_encode %{
__ shrl($dst$$Address, $shift$$constant);
%}
ins_pipe(ialu_mem_imm);
%}
// Logical Shift Right by 8-bit immediate
instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
%{
@ -9439,32 +9235,6 @@ instruct shrI_mem_rReg(rRegI dst, memory src, rRegI shift)
%}
// Long Shift Instructions
// Shift Left by one
instruct salL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (LShiftL dst shift));
effect(KILL cr);
format %{ "salq $dst, $shift" %}
ins_encode %{
__ salq($dst$$Register, $shift$$constant);
%}
ins_pipe(ialu_reg);
%}
// Shift Left by one
instruct salL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
effect(KILL cr);
format %{ "salq $dst, $shift" %}
ins_encode %{
__ salq($dst$$Address, $shift$$constant);
%}
ins_pipe(ialu_mem_imm);
%}
// Shift Left by 8-bit immediate
instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
%{
@ -9543,32 +9313,6 @@ instruct salL_mem_rReg(rRegL dst, memory src, rRegI shift)
ins_pipe(ialu_reg_mem);
%}
// Arithmetic shift right by one
instruct sarL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (RShiftL dst shift));
effect(KILL cr);
format %{ "sarq $dst, $shift" %}
ins_encode %{
__ sarq($dst$$Register, $shift$$constant);
%}
ins_pipe(ialu_reg);
%}
// Arithmetic shift right by one
instruct sarL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
effect(KILL cr);
format %{ "sarq $dst, $shift" %}
ins_encode %{
__ sarq($dst$$Address, $shift$$constant);
%}
ins_pipe(ialu_mem_imm);
%}
// Arithmetic Shift Right by 8-bit immediate
instruct sarL_rReg_imm(rRegL dst, immI shift, rFlagsReg cr)
%{
@ -9647,32 +9391,6 @@ instruct sarL_mem_rReg(rRegL dst, memory src, rRegI shift)
ins_pipe(ialu_reg_mem);
%}
// Logical shift right by one
instruct shrL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (URShiftL dst shift));
effect(KILL cr);
format %{ "shrq $dst, $shift" %}
ins_encode %{
__ shrq($dst$$Register, $shift$$constant);
%}
ins_pipe(ialu_reg);
%}
// Logical shift right by one
instruct shrL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
effect(KILL cr);
format %{ "shrq $dst, $shift" %}
ins_encode %{
__ shrq($dst$$Address, $shift$$constant);
%}
ins_pipe(ialu_mem_imm);
%}
// Logical Shift Right by 8-bit immediate
instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
%{
@ -10043,13 +9761,13 @@ instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
%}
// And Register with Immediate 255
instruct andI_rReg_imm255(rRegI dst, immI_255 src)
instruct andI_rReg_imm255(rRegI dst, rRegI src, immI_255 mask)
%{
match(Set dst (AndI dst src));
match(Set dst (AndI src mask));
format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
format %{ "movzbl $dst, $src\t# int & 0xFF" %}
ins_encode %{
__ movzbl($dst$$Register, $dst$$Register);
__ movzbl($dst$$Register, $src$$Register);
%}
ins_pipe(ialu_reg);
%}
@ -10067,13 +9785,13 @@ instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
%}
// And Register with Immediate 65535
instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
instruct andI_rReg_imm65535(rRegI dst, rRegI src, immI_65535 mask)
%{
match(Set dst (AndI dst src));
match(Set dst (AndI src mask));
format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
format %{ "movzwl $dst, $src\t# int & 0xFFFF" %}
ins_encode %{
__ movzwl($dst$$Register, $dst$$Register);
__ movzwl($dst$$Register, $src$$Register);
%}
ins_pipe(ialu_reg);
%}
@ -10124,7 +9842,7 @@ instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
match(Set dst (AndI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
ins_cost(150);
format %{ "andl $dst, $src\t# int" %}
ins_encode %{
__ andl($dst$$Register, $src$$Address);
@ -10322,7 +10040,7 @@ instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
match(Set dst (OrI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
ins_cost(150);
format %{ "orl $dst, $src\t# int" %}
ins_encode %{
__ orl($dst$$Register, $src$$Address);
@ -10415,7 +10133,7 @@ instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
match(Set dst (XorI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
ins_cost(150);
format %{ "xorl $dst, $src\t# int" %}
ins_encode %{
__ xorl($dst$$Register, $src$$Address);
@ -10482,25 +10200,27 @@ instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
%}
// And Register with Immediate 255
instruct andL_rReg_imm255(rRegL dst, immL_255 src)
instruct andL_rReg_imm255(rRegL dst, rRegL src, immL_255 mask)
%{
match(Set dst (AndL dst src));
match(Set dst (AndL src mask));
format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
format %{ "movzbl $dst, $src\t# long & 0xFF" %}
ins_encode %{
__ movzbq($dst$$Register, $dst$$Register);
// movzbl zeroes out the upper 32-bit and does not need REX.W
__ movzbl($dst$$Register, $src$$Register);
%}
ins_pipe(ialu_reg);
%}
// And Register with Immediate 65535
instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
instruct andL_rReg_imm65535(rRegL dst, rRegL src, immL_65535 mask)
%{
match(Set dst (AndL dst src));
match(Set dst (AndL src mask));
format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
format %{ "movzwl $dst, $src\t# long & 0xFFFF" %}
ins_encode %{
__ movzwq($dst$$Register, $dst$$Register);
// movzwl zeroes out the upper 32-bit and does not need REX.W
__ movzwl($dst$$Register, $src$$Register);
%}
ins_pipe(ialu_reg);
%}
@ -10524,7 +10244,7 @@ instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
match(Set dst (AndL dst (LoadL src)));
effect(KILL cr);
ins_cost(125);
ins_cost(150);
format %{ "andq $dst, $src\t# long" %}
ins_encode %{
__ andq($dst$$Register, $src$$Address);
@ -10739,7 +10459,7 @@ instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
match(Set dst (OrL dst (LoadL src)));
effect(KILL cr);
ins_cost(125);
ins_cost(150);
format %{ "orq $dst, $src\t# long" %}
ins_encode %{
__ orq($dst$$Register, $src$$Address);
@ -10836,7 +10556,7 @@ instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
match(Set dst (XorL dst (LoadL src)));
effect(KILL cr);
ins_cost(125);
ins_cost(150);
format %{ "xorq $dst, $src\t# long" %}
ins_encode %{
__ xorq($dst$$Register, $src$$Address);

129
test/micro/org/openjdk/bench/vm/compiler/x86/BasicRules.java Normal file
View File

@ -0,0 +1,129 @@
/*
* Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*/
package org.openjdk.bench.vm.compiler.x86;
import java.util.concurrent.TimeUnit;
import org.openjdk.jmh.annotations.*;
import org.openjdk.jmh.infra.Blackhole;
@BenchmarkMode(Mode.AverageTime)
@OutputTimeUnit(TimeUnit.NANOSECONDS)
@State(Scope.Benchmark)
@Fork(value = 3, jvmArgsAppend = "-XX:-UseSuperWord")
@Warmup(time = 1, timeUnit = TimeUnit.SECONDS)
@Measurement(time = 1, timeUnit = TimeUnit.SECONDS)
public class BasicRules {
static final int[] INT_ARRAY = new int[1024];
static final long[] LONG_ARRAY = new long[1024];
static final int INT_IMM = 100;
static final long LONG_IMM = 100;
@Benchmark
public void andL_rReg_imm255(Blackhole bh) {
for (int i = 0; i < LONG_ARRAY.length; i++) {
long v = LONG_ARRAY[i];
bh.consume(v);
bh.consume(v & 0xFFL);
}
}
@Benchmark
public void andL_rReg_imm65535(Blackhole bh) {
for (int i = 0; i < LONG_ARRAY.length; i++) {
long v = LONG_ARRAY[i];
bh.consume(v);
bh.consume(v & 0xFFFFL);
}
}
@Benchmark
public void add_mem_con(Blackhole bh) {
for (int i = 0; i < INT_ARRAY.length; i++) {
bh.consume(INT_ARRAY[i] + 100);
}
}
@Benchmark
public void divL_10(Blackhole bh) {
for (int i = 0; i < LONG_ARRAY.length; i++) {
bh.consume(LONG_ARRAY[i] / 10L);
}
}
@Benchmark
public void salI_rReg_1(Blackhole bh) {
for (int i = 0; i < INT_ARRAY.length; i++) {
bh.consume(INT_ARRAY[i] << 1);
}
}
@Benchmark
public void sarI_rReg_1(Blackhole bh) {
for (int i = 0; i < INT_ARRAY.length; i++) {
bh.consume(INT_ARRAY[i] >> 1);
}
}
@Benchmark
public void shrI_rReg_1(Blackhole bh) {
for (int i = 0; i < INT_ARRAY.length; i++) {
bh.consume(INT_ARRAY[i] >>> 1);
}
}
@Benchmark
public void salL_rReg_1(Blackhole bh) {
for (int i = 0; i < LONG_ARRAY.length; i++) {
bh.consume(LONG_ARRAY[i] << 1);
}
}
@Benchmark
public void sarL_rReg_1(Blackhole bh) {
for (int i = 0; i < LONG_ARRAY.length; i++) {
bh.consume(LONG_ARRAY[i] >> 1);
}
}
@Benchmark
public void shrL_rReg_1(Blackhole bh) {
for (int i = 0; i < LONG_ARRAY.length; i++) {
bh.consume(LONG_ARRAY[i] >>> 1);
}
}
@Benchmark
public void subI_rReg_imm(Blackhole bh) {
for (int i = 0; i < INT_ARRAY.length; i++) {
bh.consume(INT_ARRAY[i] - INT_IMM);
}
}
@Benchmark
public void subL_rReg_imm(Blackhole bh) {
for (int i = 0; i < LONG_ARRAY.length; i++) {
bh.consume(LONG_ARRAY[i] - LONG_IMM);
}
}
}

2
test/micro/org/openjdk/bench/vm/compiler/LeaInstruction.java → test/micro/org/openjdk/bench/vm/compiler/x86/LeaInstruction.java
View File

@ -20,7 +20,7 @@
* or visit www.oracle.com if you need additional information or have any
* questions.
*/
package org.openjdk.bench.vm.compiler;
package org.openjdk.bench.vm.compiler.x86;
import org.openjdk.jmh.annotations.*;
import org.openjdk.jmh.infra.Blackhole;