8204473: AARCH64: register post-index addressing mode is not supported directly
Reviewed-by: aph
This commit is contained in:
Dmitrij Pochepko
parent
8f5b71f3bb
commit
07e928c8ec
@ -58,6 +58,28 @@ extern "C" void entry(CodeBuffer *cb);
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static float unpack(unsigned value);
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short Assembler::SIMD_Size_in_bytes[] = {
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// T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
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8, 16, 8, 16, 8, 16, 8, 16, 16
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};
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#ifdef ASSERT
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static void asm_check(const unsigned int *insns, const unsigned int *insns1, size_t len) {
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bool ok = true;
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for (unsigned int i = 0; i < len; i++) {
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if (insns[i] != insns1[i]) {
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ok = false;
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printf("Ours:\n");
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Disassembler::decode((address)&insns1[i], (address)&insns1[i+1]);
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printf("Theirs:\n");
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Disassembler::decode((address)&insns[i], (address)&insns[i+1]);
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printf("\n");
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}
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}
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assert(ok, "Assembler smoke test failed");
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}
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#endif // ASSERT
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void entry(CodeBuffer *cb) {
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// {
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@ -1155,31 +1177,24 @@ Disassembly of section .text:
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};
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// END Generated code -- do not edit
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asm_check((unsigned int *)entry, insns, sizeof insns / sizeof insns[0]);
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{
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bool ok = true;
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unsigned int *insns1 = (unsigned int *)entry;
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for (unsigned int i = 0; i < sizeof insns / sizeof insns[0]; i++) {
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if (insns[i] != insns1[i]) {
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ok = false;
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printf("Ours:\n");
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Disassembler::decode((address)&insns1[i], (address)&insns1[i+1]);
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printf("Theirs:\n");
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Disassembler::decode((address)&insns[i], (address)&insns[i+1]);
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printf("\n");
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}
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}
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assert(ok, "Assembler smoke test failed");
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address PC = __ pc();
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__ ld1(v0, __ T16B, Address(r16)); // No offset
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__ ld1(v0, __ T8H, __ post(r16, 16)); // Post-index
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__ ld2(v0, v1, __ T8H, __ post(r24, 16 * 2)); // Post-index
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__ ld1(v0, __ T16B, __ post(r16, r17)); // Register post-index
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static const unsigned int vector_insns[] = {
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0x4c407200, // ld1 {v0.16b}, [x16]
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0x4cdf7600, // ld1 {v0.8h}, [x16], #16
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0x4cdf8700, // ld2 {v0.8h, v1.8h}, [x24], #32
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0x4cd17200, // ld1 {v0.16b}, [x16], x17
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};
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asm_check((unsigned int *)PC, vector_insns,
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sizeof vector_insns / sizeof vector_insns[0]);
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}
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#ifndef PRODUCT
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address PC = __ pc();
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__ ld1(v0, __ T16B, Address(r16)); // No offset
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__ ld1(v0, __ T16B, __ post(r16, 0)); // Post-index
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__ ld1(v0, __ T16B, Address(r16, r17)); //
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#endif // PRODUCT
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#endif // ASSERT
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}
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@ -305,8 +305,11 @@ public:
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Pre(Register reg, int o) : PrePost(reg, o) { }
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};
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class Post : public PrePost {
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Register _idx;
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public:
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Post(Register reg, int o) : PrePost(reg, o) { }
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Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; }
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Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; }
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Register idx_reg() { return _idx; }
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};
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namespace ext
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@ -341,7 +344,7 @@ static inline unsigned long uabs(int n) { return uabs((unsigned int)n); }
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class Address {
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public:
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enum mode { no_mode, base_plus_offset, pre, post, pcrel,
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enum mode { no_mode, base_plus_offset, pre, post, post_reg, pcrel,
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base_plus_offset_reg, literal };
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// Shift and extend for base reg + reg offset addressing
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@ -413,7 +416,8 @@ class Address {
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Address(Pre p)
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: _mode(pre), _base(p.reg()), _offset(p.offset()) { }
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Address(Post p)
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: _mode(post), _base(p.reg()), _offset(p.offset()), _target(0) { }
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: _mode(p.idx_reg() == NULL ? post : post_reg), _base(p.reg()),
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_offset(p.offset()), _target(0), _index(p.idx_reg()) { }
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Address(address target, RelocationHolder const& rspec)
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: _mode(literal),
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_rspec(rspec),
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@ -436,7 +440,7 @@ class Address {
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Register base() const {
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guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg
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| _mode == post),
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| _mode == post | _mode == post_reg),
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"wrong mode");
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return _base;
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}
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@ -660,10 +664,14 @@ public:
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return adjust(base, offset, true);
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}
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Address post (Register base, int offset) {
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Address post(Register base, int offset) {
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return adjust(base, offset, false);
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}
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Address post(Register base, Register idx) {
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return Address(Post(base, idx));
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}
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Instruction_aarch64* current;
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void set_current(Instruction_aarch64* i) { current = i; }
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@ -2032,6 +2040,10 @@ public:
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B, H, S, D, Q
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};
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private:
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static short SIMD_Size_in_bytes[];
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public:
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#define INSN(NAME, op) \
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void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \
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ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
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@ -2051,7 +2063,8 @@ public:
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f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
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}
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void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
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int imm, int op1, int op2) {
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int imm, int op1, int op2, int regs) {
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guarantee(T <= T1Q && imm == SIMD_Size_in_bytes[T] * regs, "bad offset");
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starti;
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f(0,31), f((int)T & 1, 30);
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f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
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@ -2065,34 +2078,34 @@ public:
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f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
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}
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void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2) {
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switch (a.getMode()) {
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case Address::base_plus_offset:
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guarantee(a.offset() == 0, "no offset allowed here");
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ld_st(Vt, T, a.base(), op1, op2);
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break;
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case Address::post:
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ld_st(Vt, T, a.base(), a.offset(), op1, op2);
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break;
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case Address::base_plus_offset_reg:
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ld_st(Vt, T, a.base(), a.index(), op1, op2);
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break;
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default:
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ShouldNotReachHere();
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}
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}
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void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2, int regs) {
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switch (a.getMode()) {
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case Address::base_plus_offset:
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guarantee(a.offset() == 0, "no offset allowed here");
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ld_st(Vt, T, a.base(), op1, op2);
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break;
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case Address::post:
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ld_st(Vt, T, a.base(), a.offset(), op1, op2, regs);
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break;
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case Address::post_reg:
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ld_st(Vt, T, a.base(), a.index(), op1, op2);
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break;
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default:
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ShouldNotReachHere();
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}
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}
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public:
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#define INSN1(NAME, op1, op2) \
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#define INSN1(NAME, op1, op2) \
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void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \
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ld_st(Vt, T, a, op1, op2); \
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ld_st(Vt, T, a, op1, op2, 1); \
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}
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#define INSN2(NAME, op1, op2) \
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void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
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assert(Vt->successor() == Vt2, "Registers must be ordered"); \
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ld_st(Vt, T, a, op1, op2); \
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ld_st(Vt, T, a, op1, op2, 2); \
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}
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#define INSN3(NAME, op1, op2) \
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@ -2100,7 +2113,7 @@ public:
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SIMD_Arrangement T, const Address &a) { \
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assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \
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"Registers must be ordered"); \
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ld_st(Vt, T, a, op1, op2); \
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ld_st(Vt, T, a, op1, op2, 3); \
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}
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#define INSN4(NAME, op1, op2) \
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@ -2108,7 +2121,7 @@ public:
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FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \
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assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \
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Vt3->successor() == Vt4, "Registers must be ordered"); \
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ld_st(Vt, T, a, op1, op2); \
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ld_st(Vt, T, a, op1, op2, 4); \
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}
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INSN1(ld1, 0b001100010, 0b0111);
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