8309332: RISC-V: Improve PrintOptoAssembly output of vector nodes
Reviewed-by: yzhu, fyang
This commit is contained in:
Gui Cao
Fei Yang
parent
ecb17532dc
commit
08c91c2212
@ -241,8 +241,7 @@ instruct vabs(vReg dst, vReg src, vReg tmp) %{
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match(Set dst (AbsVL src));
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ins_cost(VEC_COST);
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effect(TEMP tmp);
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format %{ "vrsub.vi $tmp, $src, 0\t#@vabs\n\t"
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"vmax.vv $dst, $tmp, $src" %}
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format %{ "vabs $dst, $src\t# KILL $tmp" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -256,7 +255,7 @@ instruct vabs_fp(vReg dst, vReg src) %{
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match(Set dst (AbsVF src));
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match(Set dst (AbsVD src));
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ins_cost(VEC_COST);
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format %{ "vfsgnjx.vv $dst, $src, $src, vm\t#@vabs_fp" %}
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format %{ "vabs_fp $dst, $src" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -308,7 +307,7 @@ instruct vadd(vReg dst, vReg src1, vReg src2) %{
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match(Set dst (AddVI src1 src2));
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match(Set dst (AddVL src1 src2));
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ins_cost(VEC_COST);
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format %{ "vadd.vv $dst, $src1, $src2\t#@vadd" %}
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format %{ "vadd $dst, $src1, $src2" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -323,7 +322,7 @@ instruct vadd_fp(vReg dst, vReg src1, vReg src2) %{
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match(Set dst (AddVF src1 src2));
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match(Set dst (AddVD src1 src2));
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ins_cost(VEC_COST);
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format %{ "vfadd.vv $dst, $src1, $src2\t#@vadd_fp" %}
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format %{ "vadd_fp $dst, $src1, $src2" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -342,7 +341,7 @@ instruct vadd_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
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match(Set dst_src1 (AddVI (Binary dst_src1 src2) v0));
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match(Set dst_src1 (AddVL (Binary dst_src1 src2) v0));
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ins_cost(VEC_COST);
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format %{ "vadd.vv $dst_src1, $src2, $v0\t#@vadd_masked" %}
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format %{ "vadd_masked $dst_src1, $dst_src1, $src2, $v0" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -357,7 +356,7 @@ instruct vadd_fp_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
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match(Set dst_src1 (AddVF (Binary dst_src1 src2) v0));
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match(Set dst_src1 (AddVD (Binary dst_src1 src2) v0));
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ins_cost(VEC_COST);
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format %{ "vfadd.vv $dst_src1, $src2, $v0\t#@vadd_fp_masked" %}
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format %{ "vadd_fp_masked $dst_src1, $dst_src1, $src2, $v0" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -376,7 +375,7 @@ instruct vsub(vReg dst, vReg src1, vReg src2) %{
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match(Set dst (SubVI src1 src2));
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match(Set dst (SubVL src1 src2));
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ins_cost(VEC_COST);
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format %{ "vsub.vv $dst, $src1, $src2\t#@vsub" %}
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format %{ "vsub $dst, $src1, $src2" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -390,7 +389,7 @@ instruct vsub_fp(vReg dst, vReg src1, vReg src2) %{
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match(Set dst (SubVF src1 src2));
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match(Set dst (SubVD src1 src2));
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ins_cost(VEC_COST);
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format %{ "vfsub.vv $dst, $src1, $src2\t@vsub_fp" %}
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format %{ "vsub_fp $dst, $src1, $src2" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -408,7 +407,7 @@ instruct vsub_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
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match(Set dst_src1 (SubVI (Binary dst_src1 src2) v0));
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match(Set dst_src1 (SubVL (Binary dst_src1 src2) v0));
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ins_cost(VEC_COST);
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format %{ "vsub.vv $dst_src1, $src2, $v0\t#@vsub_masked" %}
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format %{ "vsub_masked $dst_src1, $dst_src1, $src2, $v0" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -422,7 +421,7 @@ instruct vsub_fp_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
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match(Set dst_src1 (SubVF (Binary dst_src1 src2) v0));
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match(Set dst_src1 (SubVD (Binary dst_src1 src2) v0));
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ins_cost(VEC_COST);
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format %{ "vfsub.vv $dst_src1, $src2, $v0\t#@vsub_fp_masked" %}
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format %{ "vsub_fp_masked $dst_src1, $dst_src1, $src2, $v0" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -437,7 +436,7 @@ instruct vsub_fp_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
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instruct vand(vReg dst, vReg src1, vReg src2) %{
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match(Set dst (AndV src1 src2));
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ins_cost(VEC_COST);
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format %{ "vand.vv $dst, $src1, $src2\t#@vand" %}
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format %{ "vand $dst, $src1, $src2" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -453,7 +452,7 @@ instruct vand(vReg dst, vReg src1, vReg src2) %{
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instruct vand_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
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match(Set dst_src1 (AndV (Binary dst_src1 src2) v0));
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ins_cost(VEC_COST);
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format %{ "vand_masked $dst_src1, $src2, $v0" %}
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format %{ "vand_masked $dst_src1, $dst_src1, $src2, $v0" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -469,7 +468,7 @@ instruct vand_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
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instruct vor(vReg dst, vReg src1, vReg src2) %{
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match(Set dst (OrV src1 src2));
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ins_cost(VEC_COST);
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format %{ "vor.vv $dst, $src1, $src2\t#@vor" %}
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format %{ "vor $dst, $src1, $src2" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -485,7 +484,7 @@ instruct vor(vReg dst, vReg src1, vReg src2) %{
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instruct vor_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
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match(Set dst_src1 (OrV (Binary dst_src1 src2) v0));
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ins_cost(VEC_COST);
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format %{ "vor_masked $dst_src1, $src2, $v0" %}
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format %{ "vor_masked $dst_src1, $dst_src1, $src2, $v0" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -501,7 +500,7 @@ instruct vor_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
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instruct vxor(vReg dst, vReg src1, vReg src2) %{
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match(Set dst (XorV src1 src2));
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ins_cost(VEC_COST);
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format %{ "vxor.vv $dst, $src1, $src2\t#@vxor" %}
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format %{ "vxor $dst, $src1, $src2" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -517,7 +516,7 @@ instruct vxor(vReg dst, vReg src1, vReg src2) %{
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instruct vxor_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
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match(Set dst_src1 (XorV (Binary dst_src1 src2) v0));
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ins_cost(VEC_COST);
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format %{ "vxor_masked $dst_src1, $src2, $v0" %}
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format %{ "vxor_masked $dst_src1, $dst_src1, $src2, $v0" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -534,7 +533,7 @@ instruct vdiv_fp(vReg dst, vReg src1, vReg src2) %{
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match(Set dst (DivVF src1 src2));
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match(Set dst (DivVD src1 src2));
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ins_cost(VEC_COST);
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format %{ "vfdiv.vv $dst, $src1, $src2\t#@vdiv_fp" %}
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format %{ "vdiv_fp $dst, $src1, $src2" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -551,7 +550,7 @@ instruct vdiv_fp_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
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match(Set dst_src1 (DivVF (Binary dst_src1 src2) v0));
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match(Set dst_src1 (DivVD (Binary dst_src1 src2) v0));
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ins_cost(VEC_COST);
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format %{ "vfdiv.vv $dst_src1, $src2, $v0\t#@vdiv_fp_masked" %}
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format %{ "vdiv_fp_masked $dst_src1, $dst_src1, $src2, $v0" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -569,7 +568,7 @@ instruct vmax(vReg dst, vReg src1, vReg src2) %{
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Matcher::vector_element_basic_type(n) != T_DOUBLE);
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match(Set dst (MaxV src1 src2));
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ins_cost(VEC_COST);
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format %{ "vmax.vv $dst, $src1, $src2\t#@vmax" %}
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format %{ "vmax $dst, $src1, $src2" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -584,7 +583,7 @@ instruct vmin(vReg dst, vReg src1, vReg src2) %{
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Matcher::vector_element_basic_type(n) != T_DOUBLE);
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match(Set dst (MinV src1 src2));
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ins_cost(VEC_COST);
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format %{ "vmin.vv $dst, $src1, $src2\t#@vmin" %}
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format %{ "vmin $dst, $src1, $src2" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -633,7 +632,7 @@ instruct vmaxF(vReg dst, vReg src1, vReg src2, vRegMask_V0 v0) %{
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match(Set dst (MaxV src1 src2));
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effect(TEMP_DEF dst, TEMP v0);
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ins_cost(VEC_COST);
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format %{ "vmaxF $dst, $src1, $src2\t#@vmaxF" %}
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format %{ "vmaxF $dst, $src1, $src2" %}
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ins_encode %{
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__ minmax_fp_v(as_VectorRegister($dst$$reg),
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as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg),
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@ -647,7 +646,7 @@ instruct vmaxD(vReg dst, vReg src1, vReg src2, vRegMask_V0 v0) %{
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match(Set dst (MaxV src1 src2));
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effect(TEMP_DEF dst, TEMP v0);
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ins_cost(VEC_COST);
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format %{ "vmaxD $dst, $src1, $src2\t#@vmaxD" %}
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format %{ "vmaxD $dst, $src1, $src2" %}
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ins_encode %{
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__ minmax_fp_v(as_VectorRegister($dst$$reg),
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as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg),
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@ -661,7 +660,7 @@ instruct vminF(vReg dst, vReg src1, vReg src2, vRegMask_V0 v0) %{
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match(Set dst (MinV src1 src2));
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effect(TEMP_DEF dst, TEMP v0);
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ins_cost(VEC_COST);
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format %{ "vminF $dst, $src1, $src2\t#@vminF" %}
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format %{ "vminF $dst, $src1, $src2" %}
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ins_encode %{
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__ minmax_fp_v(as_VectorRegister($dst$$reg),
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as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg),
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@ -675,7 +674,7 @@ instruct vminD(vReg dst, vReg src1, vReg src2, vRegMask_V0 v0) %{
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match(Set dst (MinV src1 src2));
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effect(TEMP_DEF dst, TEMP v0);
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ins_cost(VEC_COST);
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format %{ "vminD $dst, $src1, $src2\t#@vminD" %}
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format %{ "vminD $dst, $src1, $src2" %}
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ins_encode %{
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__ minmax_fp_v(as_VectorRegister($dst$$reg),
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as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg),
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@ -754,7 +753,7 @@ instruct vfmla(vReg dst_src1, vReg src2, vReg src3) %{
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match(Set dst_src1 (FmaVF dst_src1 (Binary src2 src3)));
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match(Set dst_src1 (FmaVD dst_src1 (Binary src2 src3)));
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ins_cost(VEC_COST);
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format %{ "vfmacc.vv $dst_src1, $src2, $src3\t#@vfmla" %}
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format %{ "vfmla $dst_src1, $dst_src1, $src2, $src3" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -771,7 +770,7 @@ instruct vfmadd_masked(vReg dst_src1, vReg src2, vReg src3, vRegMask_V0 v0) %{
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predicate(UseFMA);
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match(Set dst_src1 (FmaVF (Binary dst_src1 src2) (Binary src3 v0)));
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match(Set dst_src1 (FmaVD (Binary dst_src1 src2) (Binary src3 v0)));
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format %{ "vfmadd_masked $dst_src1, $src2, $src3, $v0" %}
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format %{ "vfmadd_masked $dst_src1, $dst_src1, $src2, $src3, $v0" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -790,7 +789,7 @@ instruct vfmlsF(vReg dst_src1, vReg src2, vReg src3) %{
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match(Set dst_src1 (FmaVF dst_src1 (Binary (NegVF src2) src3)));
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match(Set dst_src1 (FmaVF dst_src1 (Binary src2 (NegVF src3))));
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ins_cost(VEC_COST);
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format %{ "vfnmsac.vv $dst_src1, $src2, $src3\t#@vfmlsF" %}
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format %{ "vfmlsF $dst_src1, $dst_src1, $src2, $src3" %}
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ins_encode %{
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__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this));
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__ vfnmsac_vv(as_VectorRegister($dst_src1$$reg),
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@ -806,7 +805,7 @@ instruct vfmlsD(vReg dst_src1, vReg src2, vReg src3) %{
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match(Set dst_src1 (FmaVD dst_src1 (Binary (NegVD src2) src3)));
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match(Set dst_src1 (FmaVD dst_src1 (Binary src2 (NegVD src3))));
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ins_cost(VEC_COST);
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format %{ "vfnmsac.vv $dst_src1, $src2, $src3\t#@vfmlsD" %}
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format %{ "vfmlsD $dst_src1, $dst_src1, $src2, $src3" %}
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ins_encode %{
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__ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this));
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__ vfnmsac_vv(as_VectorRegister($dst_src1$$reg),
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@ -822,7 +821,7 @@ instruct vfnmsub_masked(vReg dst_src1, vReg src2, vReg src3, vRegMask_V0 v0) %{
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predicate(UseFMA);
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match(Set dst_src1 (FmaVF (Binary dst_src1 (NegVF src2)) (Binary src3 v0)));
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match(Set dst_src1 (FmaVD (Binary dst_src1 (NegVD src2)) (Binary src3 v0)));
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format %{ "vfnmsub_masked $dst_src1, $src2, $src3, $v0" %}
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format %{ "vfnmsub_masked $dst_src1, $dst_src1, $src2, $src3, $v0" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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@ -841,7 +840,7 @@ instruct vfnmlaF(vReg dst_src1, vReg src2, vReg src3) %{
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match(Set dst_src1 (FmaVF (NegVF dst_src1) (Binary (NegVF src2) src3)));
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match(Set dst_src1 (FmaVF (NegVF dst_src1) (Binary src2 (NegVF src3))));
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ins_cost(VEC_COST);
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format %{ "vfnmacc.vv $dst_src1, $src2, $src3\t#@vfnmlaF" %}
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format %{ "vfnmlaF $dst_src1, $dst_src1, $src2, $src3" %}
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ins_encode %{
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__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this));
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__ vfnmacc_vv(as_VectorRegister($dst_src1$$reg),
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@ -857,7 +856,7 @@ instruct vfnmlaD(vReg dst_src1, vReg src2, vReg src3) %{
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match(Set dst_src1 (FmaVD (NegVD dst_src1) (Binary (NegVD src2) src3)));
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match(Set dst_src1 (FmaVD (NegVD dst_src1) (Binary src2 (NegVD src3))));
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ins_cost(VEC_COST);
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format %{ "vfnmacc.vv $dst_src1, $src2, $src3\t#@vfnmlaD" %}
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format %{ "vfnmlaD $dst_src1, $dst_src1, $src2, $src3" %}
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ins_encode %{
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__ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this));
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__ vfnmacc_vv(as_VectorRegister($dst_src1$$reg),
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@ -873,7 +872,7 @@ instruct vfnmadd_masked(vReg dst_src1, vReg src2, vReg src3, vRegMask_V0 v0) %{
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predicate(UseFMA);
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match(Set dst_src1 (FmaVF (Binary dst_src1 (NegVF src2)) (Binary (NegVF src3) v0)));
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match(Set dst_src1 (FmaVD (Binary dst_src1 (NegVD src2)) (Binary (NegVD src3) v0)));
|
||||
format %{ "vfnmadd_masked $dst_src1, $src2, $src3, $v0" %}
|
||||
format %{ "vfnmadd_masked $dst_src1, $dst_src1, $src2, $src3, $v0" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length(this));
|
||||
@ -890,7 +889,7 @@ instruct vfnmlsF(vReg dst_src1, vReg src2, vReg src3) %{
|
||||
predicate(UseFMA);
|
||||
match(Set dst_src1 (FmaVF (NegVF dst_src1) (Binary src2 src3)));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vfmsac.vv $dst_src1, $src2, $src3\t#@vfnmlsF" %}
|
||||
format %{ "vfnmlsF $dst_src1, $dst_src1, $src2, $src3" %}
|
||||
ins_encode %{
|
||||
__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this));
|
||||
__ vfmsac_vv(as_VectorRegister($dst_src1$$reg),
|
||||
@ -904,7 +903,7 @@ instruct vfnmlsD(vReg dst_src1, vReg src2, vReg src3) %{
|
||||
predicate(UseFMA);
|
||||
match(Set dst_src1 (FmaVD (NegVD dst_src1) (Binary src2 src3)));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vfmsac.vv $dst_src1, $src2, $src3\t#@vfnmlsD" %}
|
||||
format %{ "vfnmlsD $dst_src1, $dst_src1, $src2, $src3" %}
|
||||
ins_encode %{
|
||||
__ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this));
|
||||
__ vfmsac_vv(as_VectorRegister($dst_src1$$reg),
|
||||
@ -920,7 +919,7 @@ instruct vfmsub_masked(vReg dst_src1, vReg src2, vReg src3, vRegMask_V0 v0) %{
|
||||
predicate(UseFMA);
|
||||
match(Set dst_src1 (FmaVF (Binary dst_src1 src2) (Binary (NegVF src3) v0)));
|
||||
match(Set dst_src1 (FmaVD (Binary dst_src1 src2) (Binary (NegVD src3) v0)));
|
||||
format %{ "vfmsub_masked $dst_src1, $src2, $src3, $v0" %}
|
||||
format %{ "vfmsub_masked $dst_src1, $dst_src1, $src2, $src3, $v0" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length(this));
|
||||
@ -939,7 +938,7 @@ instruct vmla(vReg dst_src1, vReg src2, vReg src3) %{
|
||||
match(Set dst_src1 (AddVI dst_src1 (MulVI src2 src3)));
|
||||
match(Set dst_src1 (AddVL dst_src1 (MulVL src2 src3)));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vmacc.vv $dst_src1, src2, src3\t#@vmla" %}
|
||||
format %{ "vmla $dst_src1, $dst_src1, src2, src3" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length(this));
|
||||
@ -956,7 +955,7 @@ instruct vmla_masked(vReg dst_src1, vReg src2, vReg src3, vRegMask_V0 v0) %{
|
||||
match(Set dst_src1 (AddVS (Binary dst_src1 (MulVS src2 src3)) v0));
|
||||
match(Set dst_src1 (AddVI (Binary dst_src1 (MulVI src2 src3)) v0));
|
||||
match(Set dst_src1 (AddVL (Binary dst_src1 (MulVL src2 src3)) v0));
|
||||
format %{ "vmla_masked $dst_src1, $src2, $src3, $v0" %}
|
||||
format %{ "vmla_masked $dst_src1, $dst_src1, $src2, $src3, $v0" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length(this));
|
||||
@ -975,7 +974,7 @@ instruct vmls(vReg dst_src1, vReg src2, vReg src3) %{
|
||||
match(Set dst_src1 (SubVI dst_src1 (MulVI src2 src3)));
|
||||
match(Set dst_src1 (SubVL dst_src1 (MulVL src2 src3)));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vnmsac.vv $dst_src1, src2, src3\t#@vmls" %}
|
||||
format %{ "vmls $dst_src1, $dst_src1, src2, src3" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length(this));
|
||||
@ -992,7 +991,7 @@ instruct vmls_masked(vReg dst_src1, vReg src2, vReg src3, vRegMask_V0 v0) %{
|
||||
match(Set dst_src1 (SubVS (Binary dst_src1 (MulVS src2 src3)) v0));
|
||||
match(Set dst_src1 (SubVI (Binary dst_src1 (MulVI src2 src3)) v0));
|
||||
match(Set dst_src1 (SubVL (Binary dst_src1 (MulVL src2 src3)) v0));
|
||||
format %{ "vmls_masked $dst_src1, $src2, $src3, $v0" %}
|
||||
format %{ "vmls_masked $dst_src1, $dst_src1, $src2, $src3, $v0" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length(this));
|
||||
@ -1010,7 +1009,7 @@ instruct vmul(vReg dst, vReg src1, vReg src2) %{
|
||||
match(Set dst (MulVI src1 src2));
|
||||
match(Set dst (MulVL src1 src2));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vmul.vv $dst, $src1, $src2\t#@vmul" %}
|
||||
format %{ "vmul $dst, $src1, $src2" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length(this));
|
||||
@ -1024,7 +1023,7 @@ instruct vmul_fp(vReg dst, vReg src1, vReg src2) %{
|
||||
match(Set dst (MulVF src1 src2));
|
||||
match(Set dst (MulVD src1 src2));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vfmul.vv $dst, $src1, $src2\t#@vmul_fp" %}
|
||||
format %{ "vmul_fp $dst, $src1, $src2" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length(this));
|
||||
@ -1042,7 +1041,7 @@ instruct vmul_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
|
||||
match(Set dst_src1 (MulVI (Binary dst_src1 src2) v0));
|
||||
match(Set dst_src1 (MulVL (Binary dst_src1 src2) v0));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vmul.vv $dst_src1, $src2, $v0\t#@vmul_masked" %}
|
||||
format %{ "vmul_masked $dst_src1, $dst_src1, $src2, $v0" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length(this));
|
||||
@ -1056,7 +1055,7 @@ instruct vmul_fp_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
|
||||
match(Set dst_src1 (MulVF (Binary dst_src1 src2) v0));
|
||||
match(Set dst_src1 (MulVD (Binary dst_src1 src2) v0));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vmul.vv $dst_src1, $src2, $v0\t#@vmul_fp_masked" %}
|
||||
format %{ "vmul_fp_masked $dst_src1, $dst_src1, $src2, $v0" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length(this));
|
||||
@ -1072,7 +1071,7 @@ instruct vneg(vReg dst, vReg src) %{
|
||||
match(Set dst (NegVI src));
|
||||
match(Set dst (NegVL src));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vrsub.vx $dst, $src, $src\t#@vneg" %}
|
||||
format %{ "vneg $dst, $src" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length(this));
|
||||
@ -1103,7 +1102,7 @@ instruct vfneg(vReg dst, vReg src) %{
|
||||
match(Set dst (NegVF src));
|
||||
match(Set dst (NegVD src));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vfsgnjn.vv $dst, $src, $src\t#@vfneg" %}
|
||||
format %{ "vfneg $dst, $src" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length(this));
|
||||
@ -1137,9 +1136,7 @@ instruct reduce_andI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
|
||||
match(Set dst (AndReductionV src1 src2));
|
||||
effect(TEMP tmp);
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vmv.s.x $tmp, $src1\t#@reduce_andI\n\t"
|
||||
"vredand.vs $tmp, $src2, $tmp\n\t"
|
||||
"vmv.x.s $dst, $tmp" %}
|
||||
format %{ "reduce_andI $dst, $src1, $src2\t# KILL $tmp" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this, $src2);
|
||||
__ reduce_integral_v($dst$$Register, $src1$$Register,
|
||||
@ -1154,9 +1151,7 @@ instruct reduce_andL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
|
||||
match(Set dst (AndReductionV src1 src2));
|
||||
effect(TEMP tmp);
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vmv.s.x $tmp, $src1\t#@reduce_andL\n\t"
|
||||
"vredand.vs $tmp, $src2, $tmp\n\t"
|
||||
"vmv.x.s $dst, $tmp" %}
|
||||
format %{ "reduce_andL $dst, $src1, $src2\t# KILL $tmp" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this, $src2);
|
||||
__ reduce_integral_v($dst$$Register, $src1$$Register,
|
||||
@ -1211,9 +1206,7 @@ instruct reduce_orI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
|
||||
match(Set dst (OrReductionV src1 src2));
|
||||
effect(TEMP tmp);
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vmv.s.x $tmp, $src1\t#@reduce_orI\n\t"
|
||||
"vredor.vs $tmp, $src2, $tmp\n\t"
|
||||
"vmv.x.s $dst, $tmp" %}
|
||||
format %{ "reduce_orI $dst, $src1, $src2\t# KILL $tmp" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this, $src2);
|
||||
__ reduce_integral_v($dst$$Register, $src1$$Register,
|
||||
@ -1228,9 +1221,7 @@ instruct reduce_orL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
|
||||
match(Set dst (OrReductionV src1 src2));
|
||||
effect(TEMP tmp);
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vmv.s.x $tmp, $src1\t#@reduce_orL\n\t"
|
||||
"vredor.vs $tmp, $src2, $tmp\n\t"
|
||||
"vmv.x.s $dst, $tmp" %}
|
||||
format %{ "reduce_orL $dst, $src1, $src2\t# KILL $tmp" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this, $src2);
|
||||
__ reduce_integral_v($dst$$Register, $src1$$Register,
|
||||
@ -1285,9 +1276,7 @@ instruct reduce_xorI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
|
||||
match(Set dst (XorReductionV src1 src2));
|
||||
effect(TEMP tmp);
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vmv.s.x $tmp, $src1\t#@reduce_xorI\n\t"
|
||||
"vredxor.vs $tmp, $src2, $tmp\n\t"
|
||||
"vmv.x.s $dst, $tmp" %}
|
||||
format %{ "reduce_xorI $dst, $src1, $src2\t# KILL $tmp" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this, $src2);
|
||||
__ reduce_integral_v($dst$$Register, $src1$$Register,
|
||||
@ -1302,9 +1291,7 @@ instruct reduce_xorL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
|
||||
match(Set dst (XorReductionV src1 src2));
|
||||
effect(TEMP tmp);
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vmv.s.x $tmp, $src1\t#@reduce_xorL\n\t"
|
||||
"vredxor.vs $tmp, $src2, $tmp\n\t"
|
||||
"vmv.x.s $dst, $tmp" %}
|
||||
format %{ "reduce_xorL $dst, $src1, $src2\t# KILL $tmp" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this, $src2);
|
||||
__ reduce_integral_v($dst$$Register, $src1$$Register,
|
||||
@ -1359,9 +1346,7 @@ instruct reduce_addI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
|
||||
match(Set dst (AddReductionVI src1 src2));
|
||||
effect(TEMP tmp);
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vmv.s.x $tmp, $src1\t#@reduce_addI\n\t"
|
||||
"vredsum.vs $tmp, $src2, $tmp\n\t"
|
||||
"vmv.x.s $dst, $tmp" %}
|
||||
format %{ "reduce_addI $dst, $src1, $src2\t# KILL $tmp" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this, $src2);
|
||||
__ reduce_integral_v($dst$$Register, $src1$$Register,
|
||||
@ -1376,9 +1361,7 @@ instruct reduce_addL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
|
||||
match(Set dst (AddReductionVL src1 src2));
|
||||
effect(TEMP tmp);
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vmv.s.x $tmp, $src1\t#@reduce_addL\n\t"
|
||||
"vredsum.vs $tmp, $src2, $tmp\n\t"
|
||||
"vmv.x.s $dst, $tmp" %}
|
||||
format %{ "reduce_addL $dst, $src1, $src2\t# KILL $tmp" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this, $src2);
|
||||
__ reduce_integral_v($dst$$Register, $src1$$Register,
|
||||
@ -1392,9 +1375,7 @@ instruct reduce_addF(fRegF src1_dst, vReg src2, vReg tmp) %{
|
||||
match(Set src1_dst (AddReductionVF src1_dst src2));
|
||||
effect(TEMP tmp);
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vfmv.s.f $tmp, $src1_dst\t#@reduce_addF\n\t"
|
||||
"vfredosum.vs $tmp, $src2, $tmp\n\t"
|
||||
"vfmv.f.s $src1_dst, $tmp" %}
|
||||
format %{ "reduce_addF $src1_dst, $src1_dst, $src2\t# KILL $tmp" %}
|
||||
ins_encode %{
|
||||
__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this, $src2));
|
||||
__ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1_dst$$FloatRegister);
|
||||
@ -1409,9 +1390,7 @@ instruct reduce_addD(fRegD src1_dst, vReg src2, vReg tmp) %{
|
||||
match(Set src1_dst (AddReductionVD src1_dst src2));
|
||||
effect(TEMP tmp);
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vfmv.s.f $tmp, $src1_dst\t#@reduce_addD\n\t"
|
||||
"vfredosum.vs $tmp, $src2, $tmp\n\t"
|
||||
"vfmv.f.s $src1_dst, $tmp" %}
|
||||
format %{ "reduce_addD $src1_dst, $src1_dst, $src2\t# KILL $tmp" %}
|
||||
ins_encode %{
|
||||
__ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this, $src2));
|
||||
__ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1_dst$$FloatRegister);
|
||||
@ -1462,7 +1441,7 @@ instruct reduce_addF_masked(fRegF src1_dst, vReg src2, vRegMask_V0 v0, vReg tmp)
|
||||
match(Set src1_dst (AddReductionVF (Binary src1_dst src2) v0));
|
||||
effect(TEMP tmp);
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "reduce_addF_masked $src1_dst, $src2, $v0\t# KILL $tmp" %}
|
||||
format %{ "reduce_addF_masked $src1_dst, $src1_dst, $src2, $v0\t# KILL $tmp" %}
|
||||
ins_encode %{
|
||||
__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this, $src2));
|
||||
__ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1_dst$$FloatRegister);
|
||||
@ -1477,7 +1456,7 @@ instruct reduce_addD_masked(fRegD src1_dst, vReg src2, vRegMask_V0 v0, vReg tmp)
|
||||
match(Set src1_dst (AddReductionVD (Binary src1_dst src2) v0));
|
||||
effect(TEMP tmp);
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "reduce_addD_masked $src1_dst, $src2, $v0\t# KILL $tmp" %}
|
||||
format %{ "reduce_addD_masked $src1_dst, $src1_dst, $src2, $v0\t# KILL $tmp" %}
|
||||
ins_encode %{
|
||||
__ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this, $src2));
|
||||
__ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1_dst$$FloatRegister);
|
||||
@ -1635,7 +1614,7 @@ instruct vreduce_maxF(fRegF dst, fRegF src1, vReg src2, vReg tmp1, vReg tmp2) %{
|
||||
match(Set dst (MaxReductionV src1 src2));
|
||||
ins_cost(VEC_COST);
|
||||
effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2);
|
||||
format %{ "reduce_maxF $dst, $src1, $src2, $tmp1, $tmp2" %}
|
||||
format %{ "vreduce_maxF $dst, $src1, $src2, $tmp1, $tmp2" %}
|
||||
ins_encode %{
|
||||
__ reduce_minmax_fp_v($dst$$FloatRegister,
|
||||
$src1$$FloatRegister, as_VectorRegister($src2$$reg),
|
||||
@ -1650,7 +1629,7 @@ instruct vreduce_maxD(fRegD dst, fRegD src1, vReg src2, vReg tmp1, vReg tmp2) %{
|
||||
match(Set dst (MaxReductionV src1 src2));
|
||||
ins_cost(VEC_COST);
|
||||
effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2);
|
||||
format %{ "reduce_maxD $dst, $src1, $src2, $tmp1, $tmp2" %}
|
||||
format %{ "vreduce_maxD $dst, $src1, $src2, $tmp1, $tmp2" %}
|
||||
ins_encode %{
|
||||
__ reduce_minmax_fp_v($dst$$FloatRegister,
|
||||
$src1$$FloatRegister, as_VectorRegister($src2$$reg),
|
||||
@ -1701,7 +1680,7 @@ instruct vreduce_minF(fRegF dst, fRegF src1, vReg src2, vReg tmp1, vReg tmp2) %{
|
||||
match(Set dst (MinReductionV src1 src2));
|
||||
ins_cost(VEC_COST);
|
||||
effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2);
|
||||
format %{ "reduce_minF $dst, $src1, $src2, $tmp1, $tmp2" %}
|
||||
format %{ "vreduce_minF $dst, $src1, $src2, $tmp1, $tmp2" %}
|
||||
ins_encode %{
|
||||
__ reduce_minmax_fp_v($dst$$FloatRegister,
|
||||
$src1$$FloatRegister, as_VectorRegister($src2$$reg),
|
||||
@ -1716,7 +1695,7 @@ instruct vreduce_minD(fRegD dst, fRegD src1, vReg src2, vReg tmp1, vReg tmp2) %{
|
||||
match(Set dst (MinReductionV src1 src2));
|
||||
ins_cost(VEC_COST);
|
||||
effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2);
|
||||
format %{ "reduce_minD $dst, $src1, $src2, $tmp1, $tmp2" %}
|
||||
format %{ "vreduce_minD $dst, $src1, $src2, $tmp1, $tmp2" %}
|
||||
ins_encode %{
|
||||
__ reduce_minmax_fp_v($dst$$FloatRegister,
|
||||
$src1$$FloatRegister, as_VectorRegister($src2$$reg),
|
||||
@ -1767,7 +1746,7 @@ instruct replicate(vReg dst, iRegIorL2I src) %{
|
||||
match(Set dst (ReplicateS src));
|
||||
match(Set dst (ReplicateI src));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vmv.v.x $dst, $src\t#@replicate" %}
|
||||
format %{ "replicate $dst, $src" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length(this));
|
||||
@ -1779,7 +1758,7 @@ instruct replicate(vReg dst, iRegIorL2I src) %{
|
||||
instruct replicateL(vReg dst, iRegL src) %{
|
||||
match(Set dst (ReplicateL src));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vmv.v.x $dst, $src\t#@replicateL" %}
|
||||
format %{ "replicateL $dst, $src" %}
|
||||
ins_encode %{
|
||||
__ vsetvli_helper(T_LONG, Matcher::vector_length(this));
|
||||
__ vmv_v_x(as_VectorRegister($dst$$reg), as_Register($src$$reg));
|
||||
@ -1792,7 +1771,7 @@ instruct replicate_imm5(vReg dst, immI5 con) %{
|
||||
match(Set dst (ReplicateS con));
|
||||
match(Set dst (ReplicateI con));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vmv.v.i $dst, $con\t#@replicate_imm5" %}
|
||||
format %{ "replicate_imm5 $dst, $con" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length_in_bytes(this));
|
||||
@ -1804,7 +1783,7 @@ instruct replicate_imm5(vReg dst, immI5 con) %{
|
||||
instruct replicateL_imm5(vReg dst, immL5 con) %{
|
||||
match(Set dst (ReplicateL con));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vmv.v.i $dst, $con\t#@replicateL_imm5" %}
|
||||
format %{ "replicateL_imm5 $dst, $con" %}
|
||||
ins_encode %{
|
||||
__ vsetvli_helper(T_LONG, Matcher::vector_length(this));
|
||||
__ vmv_v_i(as_VectorRegister($dst$$reg), $con$$constant);
|
||||
@ -1815,7 +1794,7 @@ instruct replicateL_imm5(vReg dst, immL5 con) %{
|
||||
instruct replicateF(vReg dst, fRegF src) %{
|
||||
match(Set dst (ReplicateF src));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vfmv.v.f $dst, $src\t#@replicateF" %}
|
||||
format %{ "replicateF $dst, $src" %}
|
||||
ins_encode %{
|
||||
__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this));
|
||||
__ vfmv_v_f(as_VectorRegister($dst$$reg), $src$$FloatRegister);
|
||||
@ -1826,7 +1805,7 @@ instruct replicateF(vReg dst, fRegF src) %{
|
||||
instruct replicateD(vReg dst, fRegD src) %{
|
||||
match(Set dst (ReplicateD src));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vfmv.v.f $dst, $src\t#@replicateD" %}
|
||||
format %{ "replicateD $dst, $src" %}
|
||||
ins_encode %{
|
||||
__ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this));
|
||||
__ vfmv_v_f(as_VectorRegister($dst$$reg), $src$$FloatRegister);
|
||||
@ -2223,7 +2202,7 @@ instruct vlsrL_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{
|
||||
instruct vasrB_imm(vReg dst, vReg src, immI shift) %{
|
||||
match(Set dst (RShiftVB src (RShiftCntV shift)));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vsra.vi $dst, $src, $shift\t#@vasrB_imm" %}
|
||||
format %{ "vasrB_imm $dst, $src, $shift" %}
|
||||
ins_encode %{
|
||||
uint32_t con = (unsigned)$shift$$constant & 0x1f;
|
||||
__ vsetvli_helper(T_BYTE, Matcher::vector_length(this));
|
||||
@ -2241,7 +2220,7 @@ instruct vasrB_imm(vReg dst, vReg src, immI shift) %{
|
||||
instruct vasrS_imm(vReg dst, vReg src, immI shift) %{
|
||||
match(Set dst (RShiftVS src (RShiftCntV shift)));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vsra.vi $dst, $src, $shift\t#@vasrS_imm" %}
|
||||
format %{ "vasrS_imm $dst, $src, $shift" %}
|
||||
ins_encode %{
|
||||
uint32_t con = (unsigned)$shift$$constant & 0x1f;
|
||||
__ vsetvli_helper(T_SHORT, Matcher::vector_length(this));
|
||||
@ -2259,7 +2238,7 @@ instruct vasrS_imm(vReg dst, vReg src, immI shift) %{
|
||||
instruct vasrI_imm(vReg dst, vReg src, immI shift) %{
|
||||
match(Set dst (RShiftVI src (RShiftCntV shift)));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vsrl.vi $dst, $src, $shift\t#@vasrI_imm" %}
|
||||
format %{ "vasrI_imm $dst, $src, $shift" %}
|
||||
ins_encode %{
|
||||
uint32_t con = (unsigned)$shift$$constant & 0x1f;
|
||||
__ vsetvli_helper(T_INT, Matcher::vector_length(this));
|
||||
@ -2277,7 +2256,7 @@ instruct vasrL_imm(vReg dst, vReg src, immI shift) %{
|
||||
predicate((n->in(2)->in(1)->get_int() & 0x3f) < 32);
|
||||
match(Set dst (RShiftVL src (RShiftCntV shift)));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vsrl.vi $dst, $src, $shift\t#@vasrL_imm" %}
|
||||
format %{ "vasrL_imm $dst, $src, $shift" %}
|
||||
ins_encode %{
|
||||
uint32_t con = (unsigned)$shift$$constant & 0x1f;
|
||||
__ vsetvli_helper(T_LONG, Matcher::vector_length(this));
|
||||
@ -2361,7 +2340,7 @@ instruct vasrL_imm_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
|
||||
instruct vlsrB_imm(vReg dst, vReg src, immI shift) %{
|
||||
match(Set dst (URShiftVB src (RShiftCntV shift)));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vsrl.vi $dst, $src, $shift\t#@vlsrB_imm" %}
|
||||
format %{ "vlsrB_imm $dst, $src, $shift" %}
|
||||
ins_encode %{
|
||||
uint32_t con = (unsigned)$shift$$constant & 0x1f;
|
||||
__ vsetvli_helper(T_BYTE, Matcher::vector_length(this));
|
||||
@ -2383,7 +2362,7 @@ instruct vlsrB_imm(vReg dst, vReg src, immI shift) %{
|
||||
instruct vlsrS_imm(vReg dst, vReg src, immI shift) %{
|
||||
match(Set dst (URShiftVS src (RShiftCntV shift)));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vsrl.vi $dst, $src, $shift\t#@vlsrS_imm" %}
|
||||
format %{ "vlsrS_imm $dst, $src, $shift" %}
|
||||
ins_encode %{
|
||||
uint32_t con = (unsigned)$shift$$constant & 0x1f;
|
||||
__ vsetvli_helper(T_SHORT, Matcher::vector_length(this));
|
||||
@ -2405,7 +2384,7 @@ instruct vlsrS_imm(vReg dst, vReg src, immI shift) %{
|
||||
instruct vlsrI_imm(vReg dst, vReg src, immI shift) %{
|
||||
match(Set dst (URShiftVI src (RShiftCntV shift)));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vsrl.vi $dst, $src, $shift\t#@vlsrI_imm" %}
|
||||
format %{ "vlsrI_imm $dst, $src, $shift" %}
|
||||
ins_encode %{
|
||||
uint32_t con = (unsigned)$shift$$constant & 0x1f;
|
||||
__ vsetvli_helper(T_INT, Matcher::vector_length(this));
|
||||
@ -2423,7 +2402,7 @@ instruct vlsrL_imm(vReg dst, vReg src, immI shift) %{
|
||||
predicate((n->in(2)->in(1)->get_int() & 0x3f) < 32);
|
||||
match(Set dst (URShiftVL src (RShiftCntV shift)));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vsrl.vi $dst, $src, $shift\t#@vlsrL_imm" %}
|
||||
format %{ "vlsrL_imm $dst, $src, $shift" %}
|
||||
ins_encode %{
|
||||
uint32_t con = (unsigned)$shift$$constant & 0x1f;
|
||||
__ vsetvli_helper(T_LONG, Matcher::vector_length(this));
|
||||
@ -2515,7 +2494,7 @@ instruct vlsrL_imm_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
|
||||
instruct vlslB_imm(vReg dst, vReg src, immI shift) %{
|
||||
match(Set dst (LShiftVB src (LShiftCntV shift)));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vsll.vi $dst, $src, $shift\t#@vlslB_imm" %}
|
||||
format %{ "vlslB_imm $dst, $src, $shift" %}
|
||||
ins_encode %{
|
||||
uint32_t con = (unsigned)$shift$$constant & 0x1f;
|
||||
__ vsetvli_helper(T_BYTE, Matcher::vector_length(this));
|
||||
@ -2532,7 +2511,7 @@ instruct vlslB_imm(vReg dst, vReg src, immI shift) %{
|
||||
instruct vlslS_imm(vReg dst, vReg src, immI shift) %{
|
||||
match(Set dst (LShiftVS src (LShiftCntV shift)));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vsll.vi $dst, $src, $shift\t#@vlslS_imm" %}
|
||||
format %{ "vlslS_imm $dst, $src, $shift" %}
|
||||
ins_encode %{
|
||||
uint32_t con = (unsigned)$shift$$constant & 0x1f;
|
||||
__ vsetvli_helper(T_SHORT, Matcher::vector_length(this));
|
||||
@ -2549,7 +2528,7 @@ instruct vlslS_imm(vReg dst, vReg src, immI shift) %{
|
||||
instruct vlslI_imm(vReg dst, vReg src, immI shift) %{
|
||||
match(Set dst (LShiftVI src (LShiftCntV shift)));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vsll.vi $dst, $src, $shift\t#@vlslI_imm" %}
|
||||
format %{ "vlslI_imm $dst, $src, $shift" %}
|
||||
ins_encode %{
|
||||
uint32_t con = (unsigned)$shift$$constant & 0x1f;
|
||||
__ vsetvli_helper(T_INT, Matcher::vector_length(this));
|
||||
@ -2562,7 +2541,7 @@ instruct vlslL_imm(vReg dst, vReg src, immI shift) %{
|
||||
predicate((n->in(2)->in(1)->get_int() & 0x3f) < 32);
|
||||
match(Set dst (LShiftVL src (LShiftCntV shift)));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vsll.vi $dst, $src, $shift\t#@vlslL_imm" %}
|
||||
format %{ "vlslL_imm $dst, $src, $shift" %}
|
||||
ins_encode %{
|
||||
uint32_t con = (unsigned)$shift$$constant & 0x1f;
|
||||
__ vsetvli_helper(T_LONG, Matcher::vector_length(this));
|
||||
@ -2654,7 +2633,7 @@ instruct vsqrt_fp(vReg dst, vReg src) %{
|
||||
match(Set dst (SqrtVF src));
|
||||
match(Set dst (SqrtVD src));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vfsqrt.v $dst, $src\t#@vsqrt_fp" %}
|
||||
format %{ "vsqrt_fp $dst, $src" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length(this));
|
||||
@ -2669,7 +2648,7 @@ instruct vsqrt_fp_masked(vReg dst_src, vRegMask_V0 v0) %{
|
||||
match(Set dst_src (SqrtVF dst_src v0));
|
||||
match(Set dst_src (SqrtVD dst_src v0));
|
||||
ins_cost(VEC_COST);
|
||||
format %{ "vsqrt_fp_masked $dst_src, $v0" %}
|
||||
format %{ "vsqrt_fp_masked $dst_src, $dst_src, $v0" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length(this));
|
||||
@ -3121,7 +3100,7 @@ instruct vmask_xor(vRegMask dst, vRegMask src1, vRegMask src2) %{
|
||||
instruct vmaskcast(vRegMask dst_src) %{
|
||||
match(Set dst_src (VectorMaskCast dst_src));
|
||||
ins_cost(0);
|
||||
format %{ "vmaskcast $dst_src\t# do nothing" %}
|
||||
format %{ "vmaskcast $dst_src, $dst_src\t# do nothing" %}
|
||||
ins_encode(/* empty encoding */);
|
||||
ins_pipe(pipe_class_empty);
|
||||
%}
|
||||
@ -3156,7 +3135,7 @@ instruct storeV_masked(vReg src, vmemA mem, vRegMask_V0 v0) %{
|
||||
|
||||
instruct vblend(vReg dst, vReg src1, vReg src2, vRegMask_V0 v0) %{
|
||||
match(Set dst (VectorBlend (Binary src1 src2) v0));
|
||||
format %{ "vmerge_vvm $dst, $src1, $src2, v0\t#@vector blend" %}
|
||||
format %{ "vblend $dst, $src1, $src2, v0" %}
|
||||
ins_encode %{
|
||||
BasicType bt = Matcher::vector_element_basic_type(this);
|
||||
__ vsetvli_helper(bt, Matcher::vector_length(this));
|
||||
@ -3432,7 +3411,7 @@ instruct reinterpret(vReg dst_src) %{
|
||||
predicate(Matcher::vector_length_in_bytes(n) == Matcher::vector_length_in_bytes(n->in(1)));
|
||||
match(Set dst_src (VectorReinterpret dst_src));
|
||||
ins_cost(0);
|
||||
format %{ "# reinterpret $dst_src\t# do nothing" %}
|
||||
format %{ "# reinterpret $dst_src, $dst_src\t# do nothing" %}
|
||||
ins_encode %{
|
||||
// empty
|
||||
%}
|
||||
@ -3467,7 +3446,7 @@ instruct vmask_reinterpret_same_esize(vRegMask dst_src) %{
|
||||
Matcher::vector_length_in_bytes(n) == Matcher::vector_length_in_bytes(n->in(1)));
|
||||
match(Set dst_src (VectorReinterpret dst_src));
|
||||
ins_cost(0);
|
||||
format %{ "vmask_reinterpret_same_esize $dst_src\t# do nothing" %}
|
||||
format %{ "vmask_reinterpret_same_esize $dst_src, $dst_src\t# do nothing" %}
|
||||
ins_encode(/* empty encoding */);
|
||||
ins_pipe(pipe_class_empty);
|
||||
%}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user