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8260501: [Vector API] Improve register usage for shift operations on x86

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Reviewed-by: vlivanov, kvn
This commit is contained in:
Jie Fu 2021-01-31 00:27:55 +00:00
parent a61ff87cd4
commit 0da9cad5f5
1 changed files with 0 additions and 2 deletions
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src/hotspot/cpu/x86/x86.ad
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@ -6011,7 +6011,6 @@ instruct vshiftI_imm(vec dst, vec src, immI8 shift) %{
match(Set dst (LShiftVI src (LShiftCntV shift)));
match(Set dst (RShiftVI src (RShiftCntV shift)));
match(Set dst (URShiftVI src (RShiftCntV shift)));
effect(TEMP dst, USE src);
format %{ "vshiftd_imm $dst,$src,$shift\t! shift packedI" %}
ins_encode %{
int opcode = this->ideal_Opcode();
@ -6058,7 +6057,6 @@ instruct vshiftL(vec dst, vec src, vec shift) %{
instruct vshiftL_imm(vec dst, vec src, immI8 shift) %{
match(Set dst (LShiftVL src (LShiftCntV shift)));
match(Set dst (URShiftVL src (RShiftCntV shift)));
effect(TEMP dst, USE src, USE shift);
format %{ "vshiftq_imm $dst,$src,$shift\t! shift packedL" %}
ins_encode %{
int opcode = this->ideal_Opcode();