From 0da9cad5f55713bc81f3a0689b8836ff548ad0cf Mon Sep 17 00:00:00 2001
From: Jie Fu <jiefu@openjdk.org>
Date: Sun, 31 Jan 2021 00:27:55 +0000
Subject: [PATCH] 8260501: [Vector API] Improve register usage for shift
 operations on x86

Reviewed-by: vlivanov, kvn
---
 src/hotspot/cpu/x86/x86.ad | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/hotspot/cpu/x86/x86.ad b/src/hotspot/cpu/x86/x86.ad
index af8ce26ddbd..3ffc7c8f06a 100644
--- a/src/hotspot/cpu/x86/x86.ad
+++ b/src/hotspot/cpu/x86/x86.ad
@@ -6011,7 +6011,6 @@ instruct vshiftI_imm(vec dst, vec src, immI8 shift) %{
   match(Set dst (LShiftVI src (LShiftCntV shift)));
   match(Set dst (RShiftVI src (RShiftCntV shift)));
   match(Set dst (URShiftVI src (RShiftCntV shift)));
-  effect(TEMP dst, USE src);
   format %{ "vshiftd_imm  $dst,$src,$shift\t! shift packedI" %}
   ins_encode %{
     int opcode = this->ideal_Opcode();
@@ -6058,7 +6057,6 @@ instruct vshiftL(vec dst, vec src, vec shift) %{
 instruct vshiftL_imm(vec dst, vec src, immI8 shift) %{
   match(Set dst (LShiftVL src (LShiftCntV shift)));
   match(Set dst (URShiftVL src (RShiftCntV shift)));
-  effect(TEMP dst, USE src, USE shift);
   format %{ "vshiftq_imm  $dst,$src,$shift\t! shift packedL" %}
   ins_encode %{
     int opcode = this->ideal_Opcode();