8230392: Define AArch64 as MULTI_COPY_ATOMIC
Reviewed-by: adinn, dholmes
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3eb71de759
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src/hotspot
@ -34,11 +34,10 @@ const bool CCallingConventionRequiresIntsAsLongs = false;
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#define SUPPORTS_NATIVE_CX8
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// Aarch64 was not originally defined as multi-copy-atomic, but now is.
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// See: "Simplifying ARM Concurrency: Multicopy-atomic Axiomatic and
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// Operational Models for ARMv8"
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// So we could #define CPU_MULTI_COPY_ATOMIC but historically we have
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// not done so.
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// Aarch64 was not originally defined to be multi-copy-atomic, but now
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// is. See: "Simplifying ARM Concurrency: Multicopy-atomic Axiomatic
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// and Operational Models for ARMv8"
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#define CPU_MULTI_COPY_ATOMIC
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// According to the ARMv8 ARM, "Concurrent modification and execution
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// of instructions can lead to the resulting instruction performing
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@ -204,11 +204,25 @@ bool OverflowTaskQueue<E, F, N>::pop_overflow(E& t)
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template<class E, MEMFLAGS F, unsigned int N>
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bool GenericTaskQueue<E, F, N>::pop_global(volatile E& t) {
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Age oldAge = _age.get();
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// Architectures with weak memory model require a barrier here
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// to guarantee that bottom is not older than age,
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// which is crucial for the correctness of the algorithm.
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#ifndef CPU_MULTI_COPY_ATOMIC
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// Architectures with non-multi-copy-atomic memory model require a
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// full fence here to guarantee that bottom is not older than age,
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// which is crucial for the correctness of the algorithm.
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//
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// We need a full fence here for this case:
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//
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// Thread1: set bottom (push)
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// Thread2: read age, read bottom, set age (pop_global)
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// Thread3: read age, read bottom (pop_global)
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//
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// The requirement is that Thread3 must never read an older bottom
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// value than Thread2 after Thread3 has seen the age value from
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// Thread2.
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OrderAccess::fence();
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#else
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// Everyone else can make do with a LoadLoad barrier to keep reads
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// from _age and _bottom in order.
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OrderAccess::loadload();
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#endif
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uint localBot = Atomic::load_acquire(&_bottom);
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uint n_elems = size(localBot, oldAge.top());
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