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8244170: [aarch64] correct instruction typo for dcps1/2/3

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Replace dpcs with dcps

Reviewed-by: adinn, phh
This commit is contained in:
Xin Liu 2020-05-19 10:38:26 -07:00
parent 554e988bea
commit 104ea2d56d
3 changed files with 5 additions and 5 deletions
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2
src/hotspot/cpu/aarch64/aarch64-asmtest.py
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@ -979,7 +979,7 @@ generate (ExtractOp, ["extrw", "extr"])
generate (CondBranchOp, ["EQ", "NE", "HS", "CS", "LO", "CC", "MI", "PL", "VS", "VC",
"HI", "LS", "GE", "LT", "GT", "LE", "AL", "NV" ])
generate (ImmOp, ["svc", "hvc", "smc", "brk", "hlt", # "dpcs1", "dpcs2", "dpcs3"
generate (ImmOp, ["svc", "hvc", "smc", "brk", "hlt", # "dcps1", "dcps2", "dcps3"
])
generate (Op, ["nop", "eret", "drps", "isb"])

2
src/hotspot/cpu/aarch64/aarch64.ad
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@ -15286,7 +15286,7 @@ instruct ShouldNotReachHere() %{
ins_encode %{
if (is_reachable()) {
__ dpcs1(0xdead + 1);
__ dcps1(0xdead + 1);
}
%}

6
src/hotspot/cpu/aarch64/assembler_aarch64.hpp
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@ -962,9 +962,9 @@ public:
INSN(smc, 0b000, 0, 0b11);
INSN(brk, 0b001, 0, 0b00);
INSN(hlt, 0b010, 0, 0b00);
INSN(dpcs1, 0b101, 0, 0b01);
INSN(dpcs2, 0b101, 0, 0b10);
INSN(dpcs3, 0b101, 0, 0b11);
INSN(dcps1, 0b101, 0, 0b01);
INSN(dcps2, 0b101, 0, 0b10);
INSN(dcps3, 0b101, 0, 0b11);
#undef INSN