From 104ea2d56d2acae66bf8358ba87f1aaed1093cc2 Mon Sep 17 00:00:00 2001
From: Xin Liu <xliu@openjdk.org>
Date: Tue, 19 May 2020 10:38:26 -0700
Subject: [PATCH] 8244170: [aarch64] correct instruction typo for dcps1/2/3

Replace dpcs with dcps

Reviewed-by: adinn, phh
---
 src/hotspot/cpu/aarch64/aarch64-asmtest.py    | 2 +-
 src/hotspot/cpu/aarch64/aarch64.ad            | 2 +-
 src/hotspot/cpu/aarch64/assembler_aarch64.hpp | 6 +++---
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/hotspot/cpu/aarch64/aarch64-asmtest.py b/src/hotspot/cpu/aarch64/aarch64-asmtest.py
index f54903041ed..5aa82cb32e4 100644
--- a/src/hotspot/cpu/aarch64/aarch64-asmtest.py
+++ b/src/hotspot/cpu/aarch64/aarch64-asmtest.py
@@ -979,7 +979,7 @@ generate (ExtractOp, ["extrw", "extr"])
 generate (CondBranchOp, ["EQ", "NE", "HS", "CS", "LO", "CC", "MI", "PL", "VS", "VC",
                         "HI", "LS", "GE", "LT", "GT", "LE", "AL", "NV" ])
 
-generate (ImmOp, ["svc", "hvc", "smc", "brk", "hlt", # "dpcs1",  "dpcs2",  "dpcs3"
+generate (ImmOp, ["svc", "hvc", "smc", "brk", "hlt", # "dcps1",  "dcps2",  "dcps3"
                ])
 
 generate (Op, ["nop", "eret", "drps", "isb"])
diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad
index c9f94e46d50..eedc825c7ca 100644
--- a/src/hotspot/cpu/aarch64/aarch64.ad
+++ b/src/hotspot/cpu/aarch64/aarch64.ad
@@ -15286,7 +15286,7 @@ instruct ShouldNotReachHere() %{
 
   ins_encode %{
     if (is_reachable()) {
-      __ dpcs1(0xdead + 1);
+      __ dcps1(0xdead + 1);
     }
   %}
 
diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp
index 5573bf423c5..1b8a4c96790 100644
--- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp
+++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp
@@ -962,9 +962,9 @@ public:
   INSN(smc, 0b000, 0, 0b11);
   INSN(brk, 0b001, 0, 0b00);
   INSN(hlt, 0b010, 0, 0b00);
-  INSN(dpcs1, 0b101, 0, 0b01);
-  INSN(dpcs2, 0b101, 0, 0b10);
-  INSN(dpcs3, 0b101, 0, 0b11);
+  INSN(dcps1, 0b101, 0, 0b01);
+  INSN(dcps2, 0b101, 0, 0b10);
+  INSN(dcps3, 0b101, 0, 0b11);
 
 #undef INSN