stan/jdk-24
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

8133842: aarch64: C2 generates illegal instructions with int shifts >=32

Browse Source 
Fix logical operatations combined with shifts >= 32

Reviewed-by: kvn, aph, adinn
This commit is contained in:
Ed Nevill 2015-08-20 09:40:08 +00:00
parent b7b1b2778c
commit 10c3342331
2 changed files with 26 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
hotspot/src/cpu/aarch64/vm/aarch64.ad
View File

@ -10041,7 +10041,7 @@ instruct AndI_reg_URShift_not_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10077,7 +10077,7 @@ instruct AndI_reg_RShift_not_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10113,7 +10113,7 @@ instruct AndI_reg_LShift_not_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10149,7 +10149,7 @@ instruct XorI_reg_URShift_not_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10185,7 +10185,7 @@ instruct XorI_reg_RShift_not_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10221,7 +10221,7 @@ instruct XorI_reg_LShift_not_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10257,7 +10257,7 @@ instruct OrI_reg_URShift_not_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10293,7 +10293,7 @@ instruct OrI_reg_RShift_not_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10329,7 +10329,7 @@ instruct OrI_reg_LShift_not_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10366,7 +10366,7 @@ instruct AndI_reg_URShift_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10404,7 +10404,7 @@ instruct AndI_reg_RShift_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10442,7 +10442,7 @@ instruct AndI_reg_LShift_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10480,7 +10480,7 @@ instruct XorI_reg_URShift_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10518,7 +10518,7 @@ instruct XorI_reg_RShift_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10556,7 +10556,7 @@ instruct XorI_reg_LShift_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10594,7 +10594,7 @@ instruct OrI_reg_URShift_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10632,7 +10632,7 @@ instruct OrI_reg_RShift_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10670,7 +10670,7 @@ instruct OrI_reg_LShift_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10708,7 +10708,7 @@ instruct AddI_reg_URShift_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10746,7 +10746,7 @@ instruct AddI_reg_RShift_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10784,7 +10784,7 @@ instruct AddI_reg_LShift_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10822,7 +10822,7 @@ instruct SubI_reg_URShift_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10860,7 +10860,7 @@ instruct SubI_reg_RShift_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@ -10898,7 +10898,7 @@ instruct SubI_reg_LShift_reg(iRegINoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
$src3$$constant & 0x3f);
$src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);

4
hotspot/src/cpu/aarch64/vm/aarch64_ad.m4
View File

@ -42,7 +42,7 @@ instruct $2$1_reg_$4_reg(iReg$1NoSp dst,
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::$5,
$src3$$constant & 0x3f);
$src3$$constant & ifelse($1,I,0x1f,0x3f));
%}
ins_pipe(ialu_reg_reg_shift);
@ -87,7 +87,7 @@ dnl into this canonical form.
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::$5,
$src3$$constant & 0x3f);
$src3$$constant & ifelse($1,I,0x1f,0x3f));
%}
ins_pipe(ialu_reg_reg_shift);