8334474: RISC-V: verify perf of ExpandBits/CompressBits (rvv)
Reviewed-by: fyang, rehn, luhenry
This commit is contained in:
Hamlin Li
parent
e29b0edc97
commit
133419177d
@ -2339,83 +2339,6 @@ void C2_MacroAssembler::signum_fp_v(VectorRegister dst, VectorRegister one, Basi
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vfsgnj_vv(dst, one, dst, v0_t);
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}
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void C2_MacroAssembler::compress_bits_v(Register dst, Register src, Register mask, bool is_long) {
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Assembler::SEW sew = is_long ? Assembler::e64 : Assembler::e32;
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// intrinsic is enabled when MaxVectorSize >= 16
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Assembler::LMUL lmul = is_long ? Assembler::m4 : Assembler::m2;
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long len = is_long ? 64 : 32;
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// load the src data(in bits) to be compressed.
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vsetivli(x0, 1, sew, Assembler::m1);
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vmv_s_x(v0, src);
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// reset the src data(in bytes) to zero.
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mv(t0, len);
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vsetvli(x0, t0, Assembler::e8, lmul);
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vmv_v_i(v4, 0);
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// convert the src data from bits to bytes.
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vmerge_vim(v4, v4, 1); // v0 as the implicit mask register
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// reset the dst data(in bytes) to zero.
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vmv_v_i(v8, 0);
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// load the mask data(in bits).
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vsetivli(x0, 1, sew, Assembler::m1);
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vmv_s_x(v0, mask);
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// compress the src data(in bytes) to dst(in bytes).
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vsetvli(x0, t0, Assembler::e8, lmul);
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vcompress_vm(v8, v4, v0);
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// convert the dst data from bytes to bits.
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vmseq_vi(v0, v8, 1);
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// store result back.
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vsetivli(x0, 1, sew, Assembler::m1);
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vmv_x_s(dst, v0);
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}
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void C2_MacroAssembler::compress_bits_i_v(Register dst, Register src, Register mask) {
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compress_bits_v(dst, src, mask, /* is_long */ false);
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}
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void C2_MacroAssembler::compress_bits_l_v(Register dst, Register src, Register mask) {
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compress_bits_v(dst, src, mask, /* is_long */ true);
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}
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void C2_MacroAssembler::expand_bits_v(Register dst, Register src, Register mask, bool is_long) {
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Assembler::SEW sew = is_long ? Assembler::e64 : Assembler::e32;
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// intrinsic is enabled when MaxVectorSize >= 16
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Assembler::LMUL lmul = is_long ? Assembler::m4 : Assembler::m2;
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long len = is_long ? 64 : 32;
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// load the src data(in bits) to be expanded.
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vsetivli(x0, 1, sew, Assembler::m1);
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vmv_s_x(v0, src);
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// reset the src data(in bytes) to zero.
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mv(t0, len);
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vsetvli(x0, t0, Assembler::e8, lmul);
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vmv_v_i(v4, 0);
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// convert the src data from bits to bytes.
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vmerge_vim(v4, v4, 1); // v0 as implicit mask register
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// reset the dst data(in bytes) to zero.
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vmv_v_i(v12, 0);
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// load the mask data(in bits).
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vsetivli(x0, 1, sew, Assembler::m1);
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vmv_s_x(v0, mask);
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// expand the src data(in bytes) to dst(in bytes).
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vsetvli(x0, t0, Assembler::e8, lmul);
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viota_m(v8, v0);
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vrgather_vv(v12, v4, v8, VectorMask::v0_t); // v0 as implicit mask register
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// convert the dst data from bytes to bits.
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vmseq_vi(v0, v12, 1);
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// store result back.
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vsetivli(x0, 1, sew, Assembler::m1);
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vmv_x_s(dst, v0);
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}
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void C2_MacroAssembler::expand_bits_i_v(Register dst, Register src, Register mask) {
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expand_bits_v(dst, src, mask, /* is_long */ false);
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}
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void C2_MacroAssembler::expand_bits_l_v(Register dst, Register src, Register mask) {
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expand_bits_v(dst, src, mask, /* is_long */ true);
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}
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// j.l.Math.round(float)
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// Returns the closest int to the argument, with ties rounding to positive infinity.
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// We need to handle 3 special cases defined by java api spec:
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@ -39,9 +39,6 @@
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VectorRegister vrs,
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bool is_latin, Label& DONE, Assembler::LMUL lmul);
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void compress_bits_v(Register dst, Register src, Register mask, bool is_long);
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void expand_bits_v(Register dst, Register src, Register mask, bool is_long);
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public:
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// Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
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void fast_lock(Register object, Register box,
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@ -184,13 +181,6 @@
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// intrinsic methods implemented by rvv instructions
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// compress bits, i.e. j.l.Integer/Long::compress.
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void compress_bits_i_v(Register dst, Register src, Register mask);
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void compress_bits_l_v(Register dst, Register src, Register mask);
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// expand bits, i.e. j.l.Integer/Long::expand.
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void expand_bits_i_v(Register dst, Register src, Register mask);
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void expand_bits_l_v(Register dst, Register src, Register mask);
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void java_round_float_v(VectorRegister dst, VectorRegister src, FloatRegister ftmp, BasicType bt, uint vector_length);
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void java_round_double_v(VectorRegister dst, VectorRegister src, FloatRegister ftmp, BasicType bt, uint vector_length);
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@ -942,26 +942,6 @@ reg_class v11_reg(
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V11, V11_H, V11_J, V11_K
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);
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// class for vector register v12
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reg_class v12_reg(
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V12, V12_H, V12_J, V12_K
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);
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// class for vector register v13
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reg_class v13_reg(
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V13, V13_H, V13_J, V13_K
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);
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// class for vector register v14
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reg_class v14_reg(
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V14, V14_H, V14_J, V14_K
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);
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// class for vector register v15
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reg_class v15_reg(
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V15, V15_H, V15_J, V15_K
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);
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// class for condition codes
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reg_class reg_flags(RFLAGS);
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@ -1896,9 +1876,6 @@ bool Matcher::match_rule_supported(int opcode) {
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}
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break;
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case Op_ExpandBits: // fall through
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case Op_CompressBits: // fall through
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guarantee(UseRVV == (MaxVectorSize >= 16), "UseRVV and MaxVectorSize not matched");
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case Op_StrCompressedCopy: // fall through
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case Op_StrInflatedCopy: // fall through
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case Op_CountPositives: // fall through
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@ -3541,46 +3518,6 @@ operand vReg_V11()
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interface(REG_INTER);
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%}
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operand vReg_V12()
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%{
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constraint(ALLOC_IN_RC(v12_reg));
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match(VecA);
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match(vReg);
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op_cost(0);
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format %{ %}
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interface(REG_INTER);
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%}
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operand vReg_V13()
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%{
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constraint(ALLOC_IN_RC(v13_reg));
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match(VecA);
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match(vReg);
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op_cost(0);
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format %{ %}
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interface(REG_INTER);
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%}
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operand vReg_V14()
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%{
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constraint(ALLOC_IN_RC(v14_reg));
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match(VecA);
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match(vReg);
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op_cost(0);
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format %{ %}
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interface(REG_INTER);
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%}
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operand vReg_V15()
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%{
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constraint(ALLOC_IN_RC(v15_reg));
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match(VecA);
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match(vReg);
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op_cost(0);
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format %{ %}
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interface(REG_INTER);
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%}
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operand vRegMask()
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%{
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constraint(ALLOC_IN_RC(vmask_reg));
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@ -3843,116 +3843,6 @@ instruct vclearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, Universe dummy,
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ins_pipe(pipe_class_memory);
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%}
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// CompressBits of Long & Integer
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instruct compressBitsI(iRegINoSp dst, iRegIorL2I src, iRegIorL2I mask, vRegMask_V0 v0,
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vReg_V4 v4, vReg_V5 v5, vReg_V8 v8, vReg_V9 v9) %{
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match(Set dst (CompressBits src mask));
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effect(TEMP v0, TEMP v4, TEMP v5, TEMP v8, TEMP v9);
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format %{ "vsetivli x0, 1, e32, m1, tu, mu\t#@compressBitsI\n\t"
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"vmv.s.x $v0, $src\n\t"
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"mv t0, 32\n\t"
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"vsetvli x0, t0, e8, m2, tu, mu\n\t"
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"vmv.v.i $v4, 0\n\t"
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"vmerge.vim $v4, $v4, 1, $v0\n\t"
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"vmv.v.i $v8, 0\n\t"
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"vsetivli x0, 1, e32, m1, tu, mu\n\t"
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"vmv.s.x $v0, $mask\n\t"
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"vsetvli x0, t0, e8, m2, tu, mu\n\t"
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"vcompress.vm $v8, $v4, $v0\n\t"
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"vmseq.vi $v0, $v8, 1\n\t"
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"vsetivli x0, 1, e32, m1, tu, mu\n\t"
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"vmv.x.s $dst, $v0\t#@compressBitsI\n\t"
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%}
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ins_encode %{
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__ compress_bits_i_v(as_Register($dst$$reg), as_Register($src$$reg), as_Register($mask$$reg));
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%}
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ins_pipe(pipe_slow);
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%}
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instruct compressBitsL(iRegLNoSp dst, iRegL src, iRegL mask, vRegMask_V0 v0,
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vReg_V4 v4, vReg_V5 v5, vReg_V6 v6, vReg_V7 v7,
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vReg_V8 v8, vReg_V9 v9, vReg_V10 v10, vReg_V11 v11) %{
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match(Set dst (CompressBits src mask));
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effect(TEMP v0, TEMP v4, TEMP v5, TEMP v6, TEMP v7, TEMP v8, TEMP v9, TEMP v10, TEMP v11);
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format %{ "vsetivli x0, 1, e64, m1, tu, mu\t#@compressBitsL\n\t"
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"vmv.s.x $v0, $src\n\t"
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"mv t0, 64\n\t"
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"vsetvli x0, t0, e8, m4, tu, mu\n\t"
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"vmv.v.i $v4, 0\n\t"
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"vmerge.vim $v4, $v4, 1, $v0\n\t"
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"vmv.v.i $v8, 0\n\t"
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"vsetivli x0, 1, e64, m1, tu, mu\n\t"
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"vmv.s.x $v0, $mask\n\t"
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"vsetvli x0, t0, e8, m4, tu, mu\n\t"
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"vcompress.vm $v8, $v4, $v0\n\t"
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"vmseq.vi $v0, $v8, 1\n\t"
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"vsetivli x0, 1, e64, m1, tu, mu\n\t"
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"vmv.x.s $dst, $v0\t#@compressBitsL\n\t"
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%}
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ins_encode %{
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__ compress_bits_l_v(as_Register($dst$$reg), as_Register($src$$reg), as_Register($mask$$reg));
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%}
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ins_pipe(pipe_slow);
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%}
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// ExpandBits of Long & Integer
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instruct expandBitsI(iRegINoSp dst, iRegIorL2I src, iRegIorL2I mask, vRegMask_V0 v0,
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vReg_V4 v4, vReg_V5 v5, vReg_V8 v8, vReg_V9 v9, vReg_V12 v12, vReg_V13 v13) %{
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match(Set dst (ExpandBits src mask));
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effect(TEMP v0, TEMP v4, TEMP v5, TEMP v8, TEMP v9, TEMP v12, TEMP v13);
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format %{ "vsetivli x0, 1, e32, m1, tu, mu\t#@expandBitsI\n\t"
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"vmv.s.x $v0, $src\n\t"
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"mv t0, 32\n\t"
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"vsetvli x0, t0, e8, m2, tu, mu\n\t"
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"vmv.v.i $v4, 0\n\t"
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"vmerge.vim $v4, $v4, 1, $v0\n\t"
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"vmv.v.i $v12, 0\n\t"
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"vsetivli x0, 1, e32, m1, tu, mu\n\t"
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"vmv.s.x $v0, $mask\n\t"
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"vsetvli x0, t0, e8, m2, tu, mu\n\t"
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"viota.m $v8, $v0\n\t"
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"vrgather.vv $v12, $v4, $v8, $v0.t\n\t"
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"vmseq.vi $v0, $v12, 1\n\t"
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"vsetivli x0, 1, e32, m1, tu, mu\n\t"
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"vmv.x.s $dst, $v0\t#@expandBitsI\n\t"
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%}
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ins_encode %{
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__ expand_bits_i_v(as_Register($dst$$reg), as_Register($src$$reg), as_Register($mask$$reg));
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%}
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ins_pipe(pipe_slow);
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%}
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instruct expandBitsL(iRegLNoSp dst, iRegL src, iRegL mask, vRegMask_V0 v0,
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vReg_V4 v4, vReg_V5 v5, vReg_V6 v6, vReg_V7 v7,
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vReg_V8 v8, vReg_V9 v9, vReg_V10 v10, vReg_V11 v11,
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vReg_V12 v12, vReg_V13 v13, vReg_V14 v14, vReg_V15 v15) %{
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match(Set dst (ExpandBits src mask));
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effect(TEMP v0, TEMP v4, TEMP v5, TEMP v6, TEMP v7, TEMP v8, TEMP v9, TEMP v10, TEMP v11,
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TEMP v12, TEMP v13, TEMP v14, TEMP v15);
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format %{ "vsetivli x0, 1, e64, m1, tu, mu\t#@expandBitsL\n\t"
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"vmv.s.x $v0, $src\n\t"
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"mv t0, 64\n\t"
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"vsetvli x0, t0, e8, m4, tu, mu\n\t"
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"vmv.v.i $v4, 0\n\t"
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"vmerge.vim $v4, $v4, 1, $v0\n\t"
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"vmv.v.i $v12, 0\n\t"
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"vsetivli x0, 1, e64, m1, tu, mu\n\t"
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"vmv.s.x $v0, $mask\n\t"
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"vsetvli x0, t0, e8, m4, tu, mu\n\t"
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"viota.m $v8, $v0\n\t"
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"vrgather.vv $v12, $v4, $v8, $v0.t\n\t"
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"vmseq.vi $v0, $v12, 1\n\t"
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"vsetivli x0, 1, e64, m1, tu, mu\n\t"
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"vmv.x.s $dst, $v0\t#@expandBitsL\n\t"
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%}
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ins_encode %{
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__ expand_bits_l_v(as_Register($dst$$reg), as_Register($src$$reg), as_Register($mask$$reg));
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%}
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ins_pipe(pipe_slow);
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%}
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// Vector Load Const
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instruct vloadcon(vReg dst, immI0 src) %{
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match(Set dst (VectorLoadConst src));
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@ -30,8 +30,7 @@
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* @requires (((os.arch=="x86" | os.arch=="amd64" | os.arch=="x86_64") &
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* (vm.cpu.features ~= ".*bmi2.*" & vm.cpu.features ~= ".*bmi1.*" &
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* vm.cpu.features ~= ".*sse2.*")) |
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* (os.arch=="aarch64" & vm.cpu.features ~= ".*svebitperm.*") |
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* (os.arch=="riscv64" & vm.cpu.features ~= ".*rvv.*"))
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* (os.arch=="aarch64" & vm.cpu.features ~= ".*svebitperm.*"))
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* @library /test/lib /
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* @run driver compiler.intrinsics.TestBitShuffleOpers
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*/
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