8269516: AArch64: Assembler cleanups
Reviewed-by: ngasson, adinn
This commit is contained in:
parent
a96012a7af
commit
1810b1c2ad
src/hotspot
@ -134,7 +134,16 @@ void Assembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset)
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#undef __
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#define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
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#define starti Instruction_aarch64 current_insn(this);
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#define f current_insn.f
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#define sf current_insn.sf
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#define rf current_insn.rf
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#define srf current_insn.srf
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#define zrf current_insn.zrf
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#define prf current_insn.prf
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#define pgrf current_insn.pgrf
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#define fixed current_insn.fixed
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void Assembler::adr(Register Rd, address adr) {
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intptr_t offset = adr - pc();
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@ -156,6 +165,53 @@ void Assembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset)
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rf(Rd, 0);
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}
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// An "all-purpose" add/subtract immediate, per ARM documentation:
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// A "programmer-friendly" assembler may accept a negative immediate
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// between -(2^24 -1) and -1 inclusive, causing it to convert a
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// requested ADD operation to a SUB, or vice versa, and then encode
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// the absolute value of the immediate as for uimm24.
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void Assembler::add_sub_immediate(Instruction_aarch64 ¤t_insn,
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Register Rd, Register Rn, unsigned uimm, int op,
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int negated_op) {
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bool sets_flags = op & 1; // this op sets flags
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union {
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unsigned u;
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int imm;
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};
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u = uimm;
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bool shift = false;
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bool neg = imm < 0;
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if (neg) {
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imm = -imm;
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op = negated_op;
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}
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assert(Rd != sp || imm % 16 == 0, "misaligned stack");
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if (imm >= (1 << 11)
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&& ((imm >> 12) << 12 == imm)) {
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imm >>= 12;
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shift = true;
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}
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f(op, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10);
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// add/subtract immediate ops with the S bit set treat r31 as zr;
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// with S unset they use sp.
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if (sets_flags)
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zrf(Rd, 0);
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else
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srf(Rd, 0);
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srf(Rn, 5);
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}
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#undef f
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#undef sf
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#undef rf
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#undef srf
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#undef zrf
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#undef prf
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#undef pgrf
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#undef fixed
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#undef starti
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Address::Address(address target, relocInfo::relocType rtype) : _mode(literal){
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@ -260,43 +316,6 @@ void Assembler::wrap_label(Label &L, prfop op, prefetch_insn insn) {
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}
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}
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// An "all-purpose" add/subtract immediate, per ARM documentation:
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// A "programmer-friendly" assembler may accept a negative immediate
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// between -(2^24 -1) and -1 inclusive, causing it to convert a
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// requested ADD operation to a SUB, or vice versa, and then encode
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// the absolute value of the immediate as for uimm24.
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void Assembler::add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
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int negated_op) {
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bool sets_flags = op & 1; // this op sets flags
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union {
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unsigned u;
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int imm;
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};
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u = uimm;
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bool shift = false;
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bool neg = imm < 0;
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if (neg) {
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imm = -imm;
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op = negated_op;
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}
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assert(Rd != sp || imm % 16 == 0, "misaligned stack");
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if (imm >= (1 << 11)
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&& ((imm >> 12) << 12 == imm)) {
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imm >>= 12;
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shift = true;
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}
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f(op, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10);
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// add/subtract immediate ops with the S bit set treat r31 as zr;
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// with S unset they use sp.
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if (sets_flags)
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zrf(Rd, 0);
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else
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srf(Rd, 0);
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srf(Rn, 5);
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}
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bool Assembler::operand_valid_for_add_sub_immediate(int64_t imm) {
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bool shift = false;
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uint64_t uimm = (uint64_t)uabs((jlong)imm);
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@ -247,12 +247,12 @@ public:
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int nbits = msb - lsb + 1;
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guarantee(val < (1ULL << nbits), "Field too big for insn");
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assert_cond(msb >= lsb);
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unsigned mask = checked_cast<unsigned>(right_n_bits(nbits));
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val <<= lsb;
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mask <<= lsb;
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insn |= val;
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assert_cond((bits & mask) == 0);
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#ifdef ASSERT
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unsigned mask = checked_cast<unsigned>(right_n_bits(nbits));
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mask <<= lsb;
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assert_cond((bits & mask) == 0);
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bits |= mask;
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#endif
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}
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@ -313,7 +313,7 @@ public:
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}
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};
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#define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
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#define starti Instruction_aarch64 current_insn(this);
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class PrePost {
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int _offset;
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@ -694,46 +694,14 @@ public:
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static address locate_next_instruction(address inst);
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Instruction_aarch64* current;
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void set_current(Instruction_aarch64* i) { current = i; }
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void f(unsigned val, int msb, int lsb) {
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current->f(val, msb, lsb);
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}
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void f(unsigned val, int msb) {
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current->f(val, msb, msb);
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}
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void sf(int64_t val, int msb, int lsb) {
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current->sf(val, msb, lsb);
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}
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void rf(Register reg, int lsb) {
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current->rf(reg, lsb);
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}
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void srf(Register reg, int lsb) {
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current->srf(reg, lsb);
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}
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void zrf(Register reg, int lsb) {
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current->zrf(reg, lsb);
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}
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void rf(FloatRegister reg, int lsb) {
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current->rf(reg, lsb);
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}
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void prf(PRegister reg, int lsb) {
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current->prf(reg, lsb);
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}
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void pgrf(PRegister reg, int lsb) {
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current->pgrf(reg, lsb);
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}
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void fixed(unsigned value, unsigned mask) {
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current->fixed(value, mask);
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}
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void emit() {
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emit_long(current->get_insn());
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assert_cond(current->get_bits() == 0xffffffff);
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current = NULL;
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}
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#define f current_insn.f
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#define sf current_insn.sf
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#define rf current_insn.rf
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#define srf current_insn.srf
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#define zrf current_insn.zrf
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#define prf current_insn.prf
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#define pgrf current_insn.pgrf
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#define fixed current_insn.fixed
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typedef void (Assembler::* uncond_branch_insn)(address dest);
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typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
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@ -764,8 +732,8 @@ public:
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#undef INSN
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void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
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int negated_op);
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void add_sub_immediate(Instruction_aarch64 ¤t_insn, Register Rd, Register Rn,
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unsigned uimm, int op, int negated_op);
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// Add/subtract (immediate)
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#define INSN(NAME, decode, negated) \
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@ -777,7 +745,7 @@ public:
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\
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void NAME(Register Rd, Register Rn, unsigned imm) { \
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starti; \
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add_sub_immediate(Rd, Rn, imm, decode, negated); \
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add_sub_immediate(current_insn, Rd, Rn, imm, decode, negated); \
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}
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INSN(addsw, 0b001, 0b011);
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@ -790,7 +758,7 @@ public:
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#define INSN(NAME, decode, negated) \
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void NAME(Register Rd, Register Rn, unsigned imm) { \
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starti; \
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add_sub_immediate(Rd, Rn, imm, decode, negated); \
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add_sub_immediate(current_insn, Rd, Rn, imm, decode, negated); \
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}
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INSN(addw, 0b000, 0b010);
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@ -1092,7 +1060,7 @@ public:
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}
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void sys(int op1, int CRn, int CRm, int op2,
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Register rt = (Register)0b11111) {
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Register rt = as_Register(0b11111)) {
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system(0b01, op1, CRn, CRm, op2, rt);
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}
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@ -1361,7 +1329,7 @@ public:
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starti; \
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f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
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sf(offset, 23, 5); \
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rf((Register)Rt, 0); \
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rf(as_Register(Rt), 0); \
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}
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INSN(ldrs, 0b00, 1);
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@ -1375,7 +1343,7 @@ public:
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starti; \
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f(size, 31, 30), f(0b111100, 29, 24), f(opc, 23, 22), f(0, 21); \
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f(0, 20, 12), f(0b01, 11, 10); \
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rf(Rn, 5), rf((Register)Rt, 0); \
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rf(Rn, 5), rf(as_Register(Rt), 0); \
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}
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INSN(ldrs, 0b10, 0b01);
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@ -1408,9 +1376,9 @@ public:
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f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
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zrf(Rt2, 10), zrf(Rt1, 0);
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if (no_allocate) {
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adr.encode_nontemporal_pair(current);
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adr.encode_nontemporal_pair(¤t_insn);
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} else {
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adr.encode_pair(current);
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adr.encode_pair(¤t_insn);
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}
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}
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@ -1436,7 +1404,8 @@ public:
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#define INSN(NAME, size, p1, V, L, no_allocate) \
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void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \
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ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \
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ld_st1(size, p1, V, L, \
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as_Register(Rt1), as_Register(Rt2), adr, no_allocate); \
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}
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INSN(stps, 0b00, 0b101, 1, 0, false);
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@ -1471,7 +1440,7 @@ public:
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f(size, 31, 30);
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f(op, 23, 22); // str
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adr.encode(current);
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adr.encode(¤t_insn);
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}
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#define INSN(NAME, size, op) \
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@ -1499,7 +1468,7 @@ public:
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#define INSN(NAME, size, op) \
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void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \
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ld_st2((Register)pfop, adr, size, op); \
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ld_st2(as_Register(pfop), adr, size, op); \
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}
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INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
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@ -1510,7 +1479,7 @@ public:
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#define INSN(NAME, size, op) \
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void NAME(FloatRegister Rt, const Address &adr) { \
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ld_st2((Register)Rt, adr, size, op, 1); \
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ld_st2(as_Register(Rt), adr, size, op, 1); \
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}
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INSN(strd, 0b11, 0b00);
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@ -1547,7 +1516,7 @@ public:
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enum shift_kind { LSL, LSR, ASR, ROR };
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void op_shifted_reg(unsigned decode,
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void op_shifted_reg(Instruction_aarch64 ¤t_insn, unsigned decode,
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enum shift_kind kind, unsigned shift,
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unsigned size, unsigned op) {
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f(size, 31);
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@ -1558,14 +1527,14 @@ public:
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}
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// Logical (shifted register)
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#define INSN(NAME, size, op, N) \
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void NAME(Register Rd, Register Rn, Register Rm, \
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enum shift_kind kind = LSL, unsigned shift = 0) { \
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starti; \
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guarantee(size == 1 || shift < 32, "incorrect shift"); \
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f(N, 21); \
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zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
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op_shifted_reg(0b01010, kind, shift, size, op); \
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#define INSN(NAME, size, op, N) \
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void NAME(Register Rd, Register Rn, Register Rm, \
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enum shift_kind kind = LSL, unsigned shift = 0) { \
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starti; \
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guarantee(size == 1 || shift < 32, "incorrect shift"); \
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f(N, 21); \
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zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
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op_shifted_reg(current_insn, 0b01010, kind, shift, size, op); \
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}
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INSN(andr, 1, 0b00, 0);
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@ -1585,7 +1554,7 @@ public:
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starti; \
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f(N, 21); \
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zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
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op_shifted_reg(0b01010, kind, shift, size, op); \
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op_shifted_reg(current_insn, 0b01010, kind, shift, size, op); \
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} \
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\
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/* These instructions have no immediate form. Provide an overload so \
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@ -1632,7 +1601,7 @@ void mvnw(Register Rd, Register Rm,
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assert_cond(kind != ROR); \
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guarantee(size == 1 || shift < 32, "incorrect shift");\
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zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \
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op_shifted_reg(0b01011, kind, shift, size, op); \
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op_shifted_reg(current_insn, 0b01011, kind, shift, size, op); \
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}
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INSN(add, 1, 0b000);
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@ -1653,10 +1622,10 @@ void mvnw(Register Rd, Register Rm,
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ext::operation option, int amount = 0) { \
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starti; \
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zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \
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add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
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add_sub_extended_reg(current_insn, op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
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}
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void add_sub_extended_reg(unsigned op, unsigned decode,
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void add_sub_extended_reg(Instruction_aarch64 ¤t_insn, unsigned op, unsigned decode,
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Register Rd, Register Rn, Register Rm,
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unsigned opt, ext::operation option, unsigned imm) {
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guarantee(imm <= 4, "shift amount must be <= 4");
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@ -1676,7 +1645,7 @@ void mvnw(Register Rd, Register Rm,
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ext::operation option, int amount = 0) { \
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starti; \
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zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \
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add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
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add_sub_extended_reg(current_insn, op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
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}
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INSN(addsw, 0b001);
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@ -1777,7 +1746,7 @@ void mvnw(Register Rd, Register Rm,
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}
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#define INSN(NAME, op, op2) \
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void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
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void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
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conditional_select(op, op2, Rd, Rn, Rm, cond); \
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}
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@ -1793,7 +1762,7 @@ void mvnw(Register Rd, Register Rm,
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#undef INSN
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// Data processing
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void data_processing(unsigned op29, unsigned opcode,
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void data_processing(Instruction_aarch64 ¤t_insn, unsigned op29, unsigned opcode,
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Register Rd, Register Rn) {
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f(op29, 31, 29), f(0b11010110, 28, 21);
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f(opcode, 15, 10);
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@ -1801,11 +1770,11 @@ void mvnw(Register Rd, Register Rm,
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}
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// (1 source)
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#define INSN(NAME, op29, opcode2, opcode) \
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void NAME(Register Rd, Register Rn) { \
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starti; \
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f(opcode2, 20, 16); \
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data_processing(op29, opcode, Rd, Rn); \
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#define INSN(NAME, op29, opcode2, opcode) \
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void NAME(Register Rd, Register Rn) { \
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starti; \
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f(opcode2, 20, 16); \
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data_processing(current_insn, op29, opcode, Rd, Rn); \
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}
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INSN(rbitw, 0b010, 0b00000, 0b00000);
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@ -1824,11 +1793,11 @@ void mvnw(Register Rd, Register Rm,
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#undef INSN
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// (2 sources)
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#define INSN(NAME, op29, opcode) \
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void NAME(Register Rd, Register Rn, Register Rm) { \
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starti; \
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rf(Rm, 16); \
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data_processing(op29, opcode, Rd, Rn); \
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#define INSN(NAME, op29, opcode) \
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void NAME(Register Rd, Register Rn, Register Rm) { \
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starti; \
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rf(Rm, 16); \
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data_processing(current_insn, op29, opcode, Rd, Rn); \
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}
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INSN(udivw, 0b000, 0b000010);
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@ -1873,9 +1842,9 @@ void mvnw(Register Rd, Register Rm,
|
||||
|
||||
#undef INSN
|
||||
|
||||
#define INSN(NAME, op54, op31, o0) \
|
||||
void NAME(Register Rd, Register Rn, Register Rm) { \
|
||||
data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \
|
||||
#define INSN(NAME, op54, op31, o0) \
|
||||
void NAME(Register Rd, Register Rn, Register Rm) { \
|
||||
data_processing(op54, op31, o0, Rd, Rn, Rm, as_Register(31)); \
|
||||
}
|
||||
|
||||
INSN(smulh, 0b100, 0b010, 0);
|
||||
@ -2054,7 +2023,7 @@ public:
|
||||
|
||||
#define INSN(NAME, op31, type, rmode, opcode) \
|
||||
void NAME(Register Rd, FloatRegister Vn) { \
|
||||
float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \
|
||||
float_int_convert(op31, type, rmode, opcode, Rd, as_Register(Vn)); \
|
||||
}
|
||||
|
||||
INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000);
|
||||
@ -2071,7 +2040,7 @@ public:
|
||||
|
||||
#define INSN(NAME, op31, type, rmode, opcode) \
|
||||
void NAME(FloatRegister Vd, Register Rn) { \
|
||||
float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \
|
||||
float_int_convert(op31, type, rmode, opcode, as_Register(Vd), Rn); \
|
||||
}
|
||||
|
||||
INSN(fmovs, 0b000, 0b00, 0b00, 0b111);
|
||||
@ -2126,7 +2095,7 @@ public:
|
||||
// Floating-point compare
|
||||
void float_compare(unsigned op31, unsigned type,
|
||||
unsigned op, unsigned op2,
|
||||
FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) {
|
||||
FloatRegister Vn, FloatRegister Vm = as_FloatRegister(0)) {
|
||||
starti;
|
||||
f(op31, 31, 29);
|
||||
f(0b11110, 28, 24);
|
||||
@ -2256,10 +2225,10 @@ private:
|
||||
static short SIMD_Size_in_bytes[];
|
||||
|
||||
public:
|
||||
#define INSN(NAME, op) \
|
||||
void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \
|
||||
ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
|
||||
} \
|
||||
#define INSN(NAME, op) \
|
||||
void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \
|
||||
ld_st2(as_Register(Rt), adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
|
||||
}
|
||||
|
||||
INSN(ldr, 1);
|
||||
INSN(str, 0);
|
||||
@ -3265,9 +3234,19 @@ inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
|
||||
}
|
||||
|
||||
Instruction_aarch64::~Instruction_aarch64() {
|
||||
assem->emit();
|
||||
assem->emit_int32(insn);
|
||||
assert_cond(get_bits() == 0xffffffff);
|
||||
}
|
||||
|
||||
#undef f
|
||||
#undef sf
|
||||
#undef rf
|
||||
#undef srf
|
||||
#undef zrf
|
||||
#undef prf
|
||||
#undef pgrf
|
||||
#undef fixed
|
||||
|
||||
#undef starti
|
||||
|
||||
// Invert a condition
|
||||
|
@ -45,17 +45,18 @@ bool ABIDescriptor::is_volatile_reg(FloatRegister reg) const {
|
||||
const ABIDescriptor ForeignGlobals::parse_abi_descriptor_impl(jobject jabi) const {
|
||||
oop abi_oop = JNIHandles::resolve_non_null(jabi);
|
||||
ABIDescriptor abi;
|
||||
const Register (*to_Register)(int) = as_Register;
|
||||
|
||||
objArrayOop inputStorage = cast<objArrayOop>(abi_oop->obj_field(ABI.inputStorage_offset));
|
||||
loadArray(inputStorage, INTEGER_TYPE, abi._integer_argument_registers, as_Register);
|
||||
loadArray(inputStorage, INTEGER_TYPE, abi._integer_argument_registers, to_Register);
|
||||
loadArray(inputStorage, VECTOR_TYPE, abi._vector_argument_registers, as_FloatRegister);
|
||||
|
||||
objArrayOop outputStorage = cast<objArrayOop>(abi_oop->obj_field(ABI.outputStorage_offset));
|
||||
loadArray(outputStorage, INTEGER_TYPE, abi._integer_return_registers, as_Register);
|
||||
loadArray(outputStorage, INTEGER_TYPE, abi._integer_return_registers, to_Register);
|
||||
loadArray(outputStorage, VECTOR_TYPE, abi._vector_return_registers, as_FloatRegister);
|
||||
|
||||
objArrayOop volatileStorage = cast<objArrayOop>(abi_oop->obj_field(ABI.volatileStorage_offset));
|
||||
loadArray(volatileStorage, INTEGER_TYPE, abi._integer_additional_volatile_registers, as_Register);
|
||||
loadArray(volatileStorage, INTEGER_TYPE, abi._integer_additional_volatile_registers, to_Register);
|
||||
loadArray(volatileStorage, VECTOR_TYPE, abi._vector_additional_volatile_registers, as_FloatRegister);
|
||||
|
||||
abi._stack_alignment_bytes = abi_oop->int_field(ABI.stackAlignment_offset);
|
||||
|
@ -36,7 +36,7 @@ typedef VMRegImpl* VMReg;
|
||||
class RegisterImpl;
|
||||
typedef RegisterImpl* Register;
|
||||
|
||||
inline Register as_Register(int encoding) {
|
||||
inline const Register as_Register(int encoding) {
|
||||
return (Register)(intptr_t) encoding;
|
||||
}
|
||||
|
||||
@ -53,7 +53,7 @@ class RegisterImpl: public AbstractRegisterImpl {
|
||||
Register successor() const { return as_Register(encoding() + 1); }
|
||||
|
||||
// construction
|
||||
inline friend Register as_Register(int encoding);
|
||||
inline friend const Register as_Register(int encoding);
|
||||
|
||||
VMReg as_VMReg();
|
||||
|
||||
@ -420,4 +420,8 @@ inline FloatRegister AbstractRegSet<FloatRegister>::first() {
|
||||
return first ? as_FloatRegister(exact_log2(first)) : fnoreg;
|
||||
}
|
||||
|
||||
inline Register as_Register(FloatRegister reg) {
|
||||
return as_Register(reg->encoding());
|
||||
}
|
||||
|
||||
#endif // CPU_AARCH64_REGISTER_AARCH64_HPP
|
||||
|
@ -222,7 +222,11 @@ class CodeSection {
|
||||
set_end(curr);
|
||||
}
|
||||
|
||||
void emit_int32(int32_t x) { *((int32_t*) end()) = x; set_end(end() + sizeof(int32_t)); }
|
||||
void emit_int32(int32_t x) {
|
||||
address curr = end();
|
||||
*((int32_t*) curr) = x;
|
||||
set_end(curr + sizeof(int32_t));
|
||||
}
|
||||
void emit_int32(int8_t x1, int8_t x2, int8_t x3, int8_t x4) {
|
||||
address curr = end();
|
||||
*((int8_t*) curr++) = x1;
|
||||
|
Loading…
x
Reference in New Issue
Block a user