8320995: RISC-V: C2 PopCountVI
8320996: RISC-V: C2 PopCountVL Reviewed-by: luhenry, fyang
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parent
0eff492e41
commit
1aebab780c
src/hotspot/cpu/riscv
test/hotspot/jtreg/compiler
lib/ir_framework/test
loopopts/superword
vectorization
@ -1904,6 +1904,16 @@ enum Nf {
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#undef INSN
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#define INSN(NAME, op, funct3, Vs1, funct6) \
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void NAME(VectorRegister Vd, VectorRegister Vs2, VectorMask vm = unmasked) { \
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patch_VArith(op, Vd, funct3, Vs1, Vs2, vm, funct6); \
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}
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// Vector Basic Bit-manipulation (Zvbb) Extension
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INSN(vcpop_v, 0b1010111, 0b010, 0b01110, 0b010010);
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#undef INSN
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#undef patch_VArith
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// ====================================
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@ -115,6 +115,7 @@ define_pd_global(intx, InlineSmallCode, 1000);
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product(bool, UseZtso, false, EXPERIMENTAL, "Assume Ztso memory model") \
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product(bool, UseZihintpause, false, EXPERIMENTAL, \
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"Use Zihintpause instructions") \
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product(bool, UseZvbb, false, EXPERIMENTAL, "Use Zvbb instructions") \
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product(bool, UseZvfh, false, EXPERIMENTAL, "Use Zvfh instructions") \
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product(bool, UseZvkn, false, EXPERIMENTAL, \
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"Use Zvkn group extension, Zvkned, Zvknhb, Zvkb, Zvkt") \
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@ -73,6 +73,9 @@ source %{
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return false;
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}
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break;
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case Op_PopCountVL:
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case Op_PopCountVI:
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return UseZvbb;
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case Op_LoadVectorGather:
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case Op_LoadVectorGatherMasked:
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if (is_subword_type(bt)) {
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@ -3784,6 +3787,37 @@ instruct vconvF2HF(vReg dst, vReg src, vReg vtmp, vRegMask_V0 v0, iRegINoSp tmp)
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ins_pipe(pipe_slow);
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%}
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// ------------------------------ Popcount vector ------------------------------
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instruct vpopcount_mask(vReg dst, vReg src, vRegMask_V0 v0) %{
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match(Set dst (PopCountVI src v0));
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match(Set dst (PopCountVL src v0));
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ins_cost(VEC_COST);
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format %{ "vcpop_v $dst, $src, $v0\t# vcpop_v with mask" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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uint vlen = Matcher::vector_length(this);
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__ vsetvli_helper(bt, vlen);
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__ vcpop_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), Assembler::v0_t);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct vpopcount(vReg dst, vReg src) %{
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match(Set dst (PopCountVI src));
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match(Set dst (PopCountVL src));
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ins_cost(VEC_COST);
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format %{ "vcpop_v $dst, $src\t# vcpop_v without mask" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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uint vlen = Matcher::vector_length(this);
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__ vsetvli_helper(bt, vlen);
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__ vcpop_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
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%}
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ins_pipe(pipe_slow);
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%}
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// ------------------------------ Vector Load Gather ---------------------------
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instruct gather_load(vReg dst, indirect mem, vReg idx) %{
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@ -245,6 +245,12 @@ void VM_Version::initialize() {
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FLAG_SET_DEFAULT(UseChaCha20Intrinsics, false);
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}
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// UseZvbb (depends on RVV).
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if (UseZvbb && !UseRVV) {
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FLAG_SET_DEFAULT(UseZvbb, false);
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warning("Cannot enable UseZvbb on cpu without RVV support.");
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}
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// SHA's
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if (FLAG_IS_DEFAULT(UseSHA)) {
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FLAG_SET_DEFAULT(UseSHA, true);
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@ -161,6 +161,7 @@ class VM_Version : public Abstract_VM_Version {
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decl(ext_Ztso , "Ztso" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZtso)) \
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decl(ext_Zihintpause , "Zihintpause" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZihintpause)) \
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decl(ext_Zacas , "Zacas" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZacas)) \
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decl(ext_Zvbb , "Zvbb" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZvbb)) \
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decl(ext_Zvfh , "Zvfh" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZvfh)) \
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decl(ext_Zvkn , "Zvkn" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZvkn)) \
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decl(mvendorid , "VendorId" , RV_NO_FLAG_BIT, false, NO_UPDATE_DEFAULT) \
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@ -102,7 +102,9 @@ public class IREncodingPrinter {
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// AArch64
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"sha3",
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"asimd",
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"sve"
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"sve",
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// Riscv64
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"zvbb"
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));
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public IREncodingPrinter() {
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2023, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2023, 2024, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -144,6 +144,11 @@ public class TestGeneralizedReductions {
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applyIfAnd = {"SuperWordReductions", "true","UsePopCountInstruction", "true"},
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counts = {IRNode.ADD_REDUCTION_VI, ">= 1",
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IRNode.POPCOUNT_VL, ">= 1"})
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@IR(applyIfPlatform = {"riscv64", "true"},
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applyIfCPUFeature = {"zvbb", "true"},
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applyIfAnd = {"SuperWordReductions", "true","UsePopCountInstruction", "true"},
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counts = {IRNode.ADD_REDUCTION_VI, ">= 1",
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IRNode.POPCOUNT_VL, ">= 1"})
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private static long testMapReductionOnGlobalAccumulator(long[] array) {
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acc = 0;
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for (int i = 0; i < array.length; i++) {
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2018, 2024, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -40,18 +40,22 @@ public class TestPopCountVector {
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public static void main(String args[]) {
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TestPopCountVector test = new TestPopCountVector();
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int err = 0;
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for (int i = 0; i < 10_000; ++i) {
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test.vectorizeBitCount();
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}
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System.out.println("Checking popcount result");
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test.checkResult();
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err += test.checkResult();
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for (int i = 0; i < 10_000; ++i) {
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test.vectorizeBitCount();
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}
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System.out.println("Checking popcount result");
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test.checkResult();
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err += test.checkResult();
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if (err > 0) {
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throw new RuntimeException("Error!");
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}
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}
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public TestPopCountVector() {
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@ -68,13 +72,17 @@ public class TestPopCountVector {
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}
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}
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public void checkResult() {
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public int checkResult() {
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int err = 0;
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for (int i = 0; i < LEN; ++i) {
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int expected = Integer.bitCount(input[i]);
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if (output[i] != expected) {
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throw new RuntimeException("Invalid result: output[" + i + "] = " + output[i] + " != " + expected);
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err++;
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System.err.println("Invalid result: output[" + i + "] = " + output[i] + " != " + expected +
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", input[" + i + "] == " + Integer.toBinaryString(input[i]));
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}
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}
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return err;
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}
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2022, 2024, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -26,12 +26,14 @@
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* @summary Test vectorization of popcount for Long
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* @requires vm.compiler2.enabled
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* @requires ((os.arch=="x86" | os.arch=="i386" | os.arch=="amd64" | os.arch=="x86_64") & vm.cpu.features ~= ".*avx512bw.*") |
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* os.simpleArch == "aarch64"
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* os.simpleArch == "aarch64" |
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* (os.arch == "riscv64" & vm.cpu.features ~= ".*zvbb.*")
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* @library /test/lib /
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* @run driver compiler.vectorization.TestPopCountVectorLong
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*/
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package compiler.vectorization;
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import compiler.lib.ir_framework.*;
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import java.util.Random;
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@ -62,16 +64,22 @@ public class TestPopCountVectorLong {
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for (int i = 0; i < LEN; ++i) {
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output[i] = Long.bitCount(input[i]);
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}
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checkResult();
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if (checkResult() > 0) {
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throw new RuntimeException("Error!");
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}
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}
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public void checkResult() {
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public int checkResult() {
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int err = 0;
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for (int i = 0; i < LEN; ++i) {
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int expected = Long.bitCount(input[i]);
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if (output[i] != expected) {
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throw new RuntimeException("Invalid result: output[" + i + "] = " + output[i] + " != " + expected);
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err++;
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System.err.println("Invalid result: output[" + i + "] = " + output[i] + " != " + expected +
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", input[" + i + "] == " + Long.toBinaryString(input[i]));
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}
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}
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return err;
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}
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}
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