8214961: AARCH64: wrong encoding for exclusive and atomic load/stores
Reviewed-by: aph
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3c0acaf846
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1f26d09d50
@ -1118,7 +1118,7 @@ public:
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Register Rn, enum operand_size sz, int op, bool ordered) {
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starti;
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f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
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rf(Rs, 16), f(ordered, 15), rf(Rt2, 10), rf(Rn, 5), rf(Rt1, 0);
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rf(Rs, 16), f(ordered, 15), rf(Rt2, 10), srf(Rn, 5), rf(Rt1, 0);
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}
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void load_exclusive(Register dst, Register addr,
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@ -1247,7 +1247,7 @@ public:
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enum operand_size sz, int op1, int op2, bool a, bool r) {
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starti;
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f(sz, 31, 30), f(0b111000, 29, 24), f(a, 23), f(r, 22), f(1, 21);
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rf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), rf(Rn, 5), zrf(Rt, 0);
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rf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), srf(Rn, 5), zrf(Rt, 0);
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}
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#define INSN(NAME, NAME_A, NAME_L, NAME_AL, op1, op2) \
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