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8292575: riscv: Represent Registers as values

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Reviewed-by: yzhu, yadongwang, fyang
This commit is contained in:
Feilong Jiang 2022-08-30 09:24:37 +00:00 committed by Fei Yang
parent 4a28f3798d
commit 21a736954f
14 changed files with 427 additions and 367 deletions

156
src/hotspot/cpu/riscv/assembler_riscv.hpp

@ -50,23 +50,23 @@ class Argument {
};
// function argument(caller-save registers)
REGISTER_DECLARATION(Register, c_rarg0, x10);
REGISTER_DECLARATION(Register, c_rarg1, x11);
REGISTER_DECLARATION(Register, c_rarg2, x12);
REGISTER_DECLARATION(Register, c_rarg3, x13);
REGISTER_DECLARATION(Register, c_rarg4, x14);
REGISTER_DECLARATION(Register, c_rarg5, x15);
REGISTER_DECLARATION(Register, c_rarg6, x16);
REGISTER_DECLARATION(Register, c_rarg7, x17);
constexpr Register c_rarg0 = x10;
constexpr Register c_rarg1 = x11;
constexpr Register c_rarg2 = x12;
constexpr Register c_rarg3 = x13;
constexpr Register c_rarg4 = x14;
constexpr Register c_rarg5 = x15;
constexpr Register c_rarg6 = x16;
constexpr Register c_rarg7 = x17;
REGISTER_DECLARATION(FloatRegister, c_farg0, f10);
REGISTER_DECLARATION(FloatRegister, c_farg1, f11);
REGISTER_DECLARATION(FloatRegister, c_farg2, f12);
REGISTER_DECLARATION(FloatRegister, c_farg3, f13);
REGISTER_DECLARATION(FloatRegister, c_farg4, f14);
REGISTER_DECLARATION(FloatRegister, c_farg5, f15);
REGISTER_DECLARATION(FloatRegister, c_farg6, f16);
REGISTER_DECLARATION(FloatRegister, c_farg7, f17);
constexpr FloatRegister c_farg0 = f10;
constexpr FloatRegister c_farg1 = f11;
constexpr FloatRegister c_farg2 = f12;
constexpr FloatRegister c_farg3 = f13;
constexpr FloatRegister c_farg4 = f14;
constexpr FloatRegister c_farg5 = f15;
constexpr FloatRegister c_farg6 = f16;
constexpr FloatRegister c_farg7 = f17;
// Symbolically name the register arguments used by the Java calling convention.
// We have control over the convention for java so we can do what we please.
@ -83,32 +83,32 @@ REGISTER_DECLARATION(FloatRegister, c_farg7, f17);
// | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 |
// |------------------------------------------------------------------------|
REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
constexpr Register j_rarg0 = c_rarg1;
constexpr Register j_rarg1 = c_rarg2;
constexpr Register j_rarg2 = c_rarg3;
constexpr Register j_rarg3 = c_rarg4;
constexpr Register j_rarg4 = c_rarg5;
constexpr Register j_rarg5 = c_rarg6;
constexpr Register j_rarg6 = c_rarg7;
constexpr Register j_rarg7 = c_rarg0;
// Java floating args are passed as per C
REGISTER_DECLARATION(FloatRegister, j_farg0, f10);
REGISTER_DECLARATION(FloatRegister, j_farg1, f11);
REGISTER_DECLARATION(FloatRegister, j_farg2, f12);
REGISTER_DECLARATION(FloatRegister, j_farg3, f13);
REGISTER_DECLARATION(FloatRegister, j_farg4, f14);
REGISTER_DECLARATION(FloatRegister, j_farg5, f15);
REGISTER_DECLARATION(FloatRegister, j_farg6, f16);
REGISTER_DECLARATION(FloatRegister, j_farg7, f17);
constexpr FloatRegister j_farg0 = f10;
constexpr FloatRegister j_farg1 = f11;
constexpr FloatRegister j_farg2 = f12;
constexpr FloatRegister j_farg3 = f13;
constexpr FloatRegister j_farg4 = f14;
constexpr FloatRegister j_farg5 = f15;
constexpr FloatRegister j_farg6 = f16;
constexpr FloatRegister j_farg7 = f17;
// zero rigster
REGISTER_DECLARATION(Register, zr, x0);
constexpr Register zr = x0;
// global pointer
REGISTER_DECLARATION(Register, gp, x3);
constexpr Register gp = x3;
// thread pointer
REGISTER_DECLARATION(Register, tp, x4);
constexpr Register tp = x4;
// registers used to hold VM data either temporarily within a method
// or across method calls
@ -116,40 +116,28 @@ REGISTER_DECLARATION(Register, tp, x4);
// volatile (caller-save) registers
// current method -- must be in a call-clobbered register
REGISTER_DECLARATION(Register, xmethod, x31);
constexpr Register xmethod = x31;
// return address
REGISTER_DECLARATION(Register, ra, x1);
constexpr Register ra = x1;
// non-volatile (callee-save) registers
// stack pointer
REGISTER_DECLARATION(Register, sp, x2);
// frame pointer
REGISTER_DECLARATION(Register, fp, x8);
// base of heap
REGISTER_DECLARATION(Register, xheapbase, x27);
// constant pool cache
REGISTER_DECLARATION(Register, xcpool, x26);
// monitors allocated on stack
REGISTER_DECLARATION(Register, xmonitors, x25);
// locals on stack
REGISTER_DECLARATION(Register, xlocals, x24);
// java thread pointer
REGISTER_DECLARATION(Register, xthread, x23);
// bytecode pointer
REGISTER_DECLARATION(Register, xbcp, x22);
// Dispatch table base
REGISTER_DECLARATION(Register, xdispatch, x21);
// Java expression stack pointer
REGISTER_DECLARATION(Register, esp, x20);
// Sender's SP while in interpreter
REGISTER_DECLARATION(Register, x19_sender_sp, x19);
constexpr Register sp = x2; // stack pointer
constexpr Register fp = x8; // frame pointer
constexpr Register xheapbase = x27; // base of heap
constexpr Register xcpool = x26; // constant pool cache
constexpr Register xmonitors = x25; // monitors allocated on stack
constexpr Register xlocals = x24; // locals on stack
constexpr Register xthread = x23; // java thread pointer
constexpr Register xbcp = x22; // bytecode pointer
constexpr Register xdispatch = x21; // Dispatch table base
constexpr Register esp = x20; // Java expression stack pointer
constexpr Register x19_sender_sp = x19; // Sender's SP while in interpreter
// temporary register(caller-save registers)
REGISTER_DECLARATION(Register, t0, x5);
REGISTER_DECLARATION(Register, t1, x6);
REGISTER_DECLARATION(Register, t2, x7);
constexpr Register t0 = x5;
constexpr Register t1 = x6;
constexpr Register t2 = x7;
const Register g_INTArgReg[Argument::n_int_register_parameters_c] = {
c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5, c_rarg6, c_rarg7
@ -218,10 +206,6 @@ class Address {
bool uses(Register reg) const { return _base == reg; }
const address target() const { return _target; }
const RelocationHolder& rspec() const { return _rspec; }
~Address() {
_target = NULL;
_base = NULL;
}
};
// Convenience classes
@ -394,15 +378,15 @@ public:
}
static void patch_reg(address a, unsigned lsb, Register reg) {
patch(a, lsb + 4, lsb, reg->encoding_nocheck());
patch(a, lsb + 4, lsb, reg->raw_encoding());
}
static void patch_reg(address a, unsigned lsb, FloatRegister reg) {
patch(a, lsb + 4, lsb, reg->encoding_nocheck());
patch(a, lsb + 4, lsb, reg->raw_encoding());
}
static void patch_reg(address a, unsigned lsb, VectorRegister reg) {
patch(a, lsb + 4, lsb, reg->encoding_nocheck());
patch(a, lsb + 4, lsb, reg->raw_encoding());
}
void emit(unsigned insn) {
@ -1550,7 +1534,7 @@ enum VectorMask {
#define INSN(NAME, op, funct3, funct6) \
void NAME(VectorRegister Vd, VectorRegister Vs1, VectorRegister Vs2, VectorMask vm = unmasked) { \
patch_VArith(op, Vd, funct3, Vs1->encoding_nocheck(), Vs2, vm, funct6); \
patch_VArith(op, Vd, funct3, Vs1->raw_encoding(), Vs2, vm, funct6); \
}
// Vector Single-Width Floating-Point Fused Multiply-Add Instructions
@ -1573,7 +1557,7 @@ enum VectorMask {
#define INSN(NAME, op, funct3, funct6) \
void NAME(VectorRegister Vd, Register Rs1, VectorRegister Vs2, VectorMask vm = unmasked) { \
patch_VArith(op, Vd, funct3, Rs1->encoding_nocheck(), Vs2, vm, funct6); \
patch_VArith(op, Vd, funct3, Rs1->raw_encoding(), Vs2, vm, funct6); \
}
// Vector Single-Width Integer Multiply-Add Instructions
@ -1588,7 +1572,7 @@ enum VectorMask {
#define INSN(NAME, op, funct3, funct6) \
void NAME(VectorRegister Vd, FloatRegister Rs1, VectorRegister Vs2, VectorMask vm = unmasked) { \
patch_VArith(op, Vd, funct3, Rs1->encoding_nocheck(), Vs2, vm, funct6); \
patch_VArith(op, Vd, funct3, Rs1->raw_encoding(), Vs2, vm, funct6); \
}
// Vector Single-Width Floating-Point Fused Multiply-Add Instructions
@ -1605,7 +1589,7 @@ enum VectorMask {
#define INSN(NAME, op, funct3, funct6) \
void NAME(VectorRegister Vd, VectorRegister Vs2, VectorRegister Vs1, VectorMask vm = unmasked) { \
patch_VArith(op, Vd, funct3, Vs1->encoding_nocheck(), Vs2, vm, funct6); \
patch_VArith(op, Vd, funct3, Vs1->raw_encoding(), Vs2, vm, funct6); \
}
// Vector Single-Width Floating-Point Reduction Instructions
@ -1695,7 +1679,7 @@ enum VectorMask {
#define INSN(NAME, op, funct3, funct6) \
void NAME(VectorRegister Vd, VectorRegister Vs2, Register Rs1, VectorMask vm = unmasked) { \
patch_VArith(op, Vd, funct3, Rs1->encoding_nocheck(), Vs2, vm, funct6); \
patch_VArith(op, Vd, funct3, Rs1->raw_encoding(), Vs2, vm, funct6); \
}
// Vector Integer Divide Instructions
@ -1748,7 +1732,7 @@ enum VectorMask {
#define INSN(NAME, op, funct3, funct6) \
void NAME(VectorRegister Vd, VectorRegister Vs2, FloatRegister Rs1, VectorMask vm = unmasked) { \
patch_VArith(op, Vd, funct3, Rs1->encoding_nocheck(), Vs2, vm, funct6); \
patch_VArith(op, Vd, funct3, Rs1->raw_encoding(), Vs2, vm, funct6); \
}
// Vector Floating-Point Compare Instructions
@ -1811,7 +1795,7 @@ enum VectorMask {
#define INSN(NAME, op, funct3, vm, funct6) \
void NAME(VectorRegister Vd, VectorRegister Vs2, VectorRegister Vs1) { \
patch_VArith(op, Vd, funct3, Vs1->encoding_nocheck(), Vs2, vm, funct6); \
patch_VArith(op, Vd, funct3, Vs1->raw_encoding(), Vs2, vm, funct6); \
}
// Vector Compress Instruction
@ -1842,7 +1826,7 @@ enum VectorMask {
#define INSN(NAME, op, funct3, Vs2, vm, funct6) \
void NAME(VectorRegister Vd, FloatRegister Rs1) { \
patch_VArith(op, Vd, funct3, Rs1->encoding_nocheck(), Vs2, vm, funct6); \
patch_VArith(op, Vd, funct3, Rs1->raw_encoding(), Vs2, vm, funct6); \
}
// Floating-Point Scalar Move Instructions
@ -1854,7 +1838,7 @@ enum VectorMask {
#define INSN(NAME, op, funct3, Vs2, vm, funct6) \
void NAME(VectorRegister Vd, VectorRegister Vs1) { \
patch_VArith(op, Vd, funct3, Vs1->encoding_nocheck(), Vs2, vm, funct6); \
patch_VArith(op, Vd, funct3, Vs1->raw_encoding(), Vs2, vm, funct6); \
}
// Vector Integer Move Instructions
@ -1864,7 +1848,7 @@ enum VectorMask {
#define INSN(NAME, op, funct3, Vs2, vm, funct6) \
void NAME(VectorRegister Vd, Register Rs1) { \
patch_VArith(op, Vd, funct3, Rs1->encoding_nocheck(), Vs2, vm, funct6); \
patch_VArith(op, Vd, funct3, Rs1->raw_encoding(), Vs2, vm, funct6); \
}
// Integer Scalar Move Instructions
@ -1975,7 +1959,7 @@ enum Nf {
#define INSN(NAME, op, width, mop, mew) \
void NAME(VectorRegister Vd, Register Rs1, VectorRegister Vs2, VectorMask vm = unmasked, Nf nf = g1) { \
patch_VLdSt(op, Vd, width, Rs1, Vs2->encoding_nocheck(), vm, mop, mew, nf); \
patch_VLdSt(op, Vd, width, Rs1, Vs2->raw_encoding(), vm, mop, mew, nf); \
}
// Vector unordered indexed load instructions
@ -1993,7 +1977,7 @@ enum Nf {
#define INSN(NAME, op, width, mop, mew) \
void NAME(VectorRegister Vd, Register Rs1, Register Rs2, VectorMask vm = unmasked, Nf nf = g1) { \
patch_VLdSt(op, Vd, width, Rs1, Rs2->encoding_nocheck(), vm, mop, mew, nf); \
patch_VLdSt(op, Vd, width, Rs1, Rs2->raw_encoding(), vm, mop, mew, nf); \
}
// Vector Strided Instructions
@ -2165,22 +2149,22 @@ public:
// patch a 16-bit instruction with a general purpose register ranging [0, 31] (5 bits)
static void c_patch_reg(address a, unsigned lsb, Register reg) {
c_patch(a, lsb + 4, lsb, reg->encoding_nocheck());
c_patch(a, lsb + 4, lsb, reg->raw_encoding());
}
// patch a 16-bit instruction with a general purpose register ranging [8, 15] (3 bits)
static void c_patch_compressed_reg(address a, unsigned lsb, Register reg) {
c_patch(a, lsb + 2, lsb, reg->compressed_encoding_nocheck());
c_patch(a, lsb + 2, lsb, reg->compressed_raw_encoding());
}
// patch a 16-bit instruction with a float register ranging [0, 31] (5 bits)
static void c_patch_reg(address a, unsigned lsb, FloatRegister reg) {
c_patch(a, lsb + 4, lsb, reg->encoding_nocheck());
c_patch(a, lsb + 4, lsb, reg->raw_encoding());
}
// patch a 16-bit instruction with a float register ranging [8, 15] (3 bits)
static void c_patch_compressed_reg(address a, unsigned lsb, FloatRegister reg) {
c_patch(a, lsb + 2, lsb, reg->compressed_encoding_nocheck());
c_patch(a, lsb + 2, lsb, reg->compressed_raw_encoding());
}
// -------------- RVC Instruction Definitions --------------

4
src/hotspot/cpu/riscv/c1_Defs_riscv.hpp

@ -39,8 +39,8 @@ enum {
// registers
enum {
pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers, // number of registers used during code emission
pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers, // number of float registers used during code emission
pd_nof_cpu_regs_frame_map = Register::number_of_registers, // number of registers used during code emission
pd_nof_fpu_regs_frame_map = FloatRegister::number_of_registers, // number of float registers used during code emission
// caller saved
pd_nof_caller_save_cpu_regs_frame_map = 13, // number of registers killed by calls

2
src/hotspot/cpu/riscv/gc/z/zBarrierSetAssembler_riscv.cpp

@ -238,7 +238,7 @@ public:
} else if (vm_reg->is_FloatRegister()) {
_fp_regs += FloatRegSet::of(vm_reg->as_FloatRegister());
} else if (vm_reg->is_VectorRegister()) {
const VMReg vm_reg_base = OptoReg::as_VMReg(opto_reg & ~(VectorRegisterImpl::max_slots_per_register - 1));
const VMReg vm_reg_base = OptoReg::as_VMReg(opto_reg & ~(VectorRegister::max_slots_per_register - 1));
_vp_regs += VectorRegSet::of(vm_reg_base->as_VectorRegister());
} else {
fatal("Unknown register type");

4
src/hotspot/cpu/riscv/interp_masm_riscv.cpp

@ -548,11 +548,11 @@ void InterpreterMacroAssembler::dispatch_only(TosState state, bool generate_poll
}
void InterpreterMacroAssembler::dispatch_only_normal(TosState state, Register Rs) {
dispatch_base(state, Interpreter::normal_table(state), Rs);
dispatch_base(state, Interpreter::normal_table(state), true, false, Rs);
}
void InterpreterMacroAssembler::dispatch_only_noverify(TosState state, Register Rs) {
dispatch_base(state, Interpreter::normal_table(state), false, Rs);
dispatch_base(state, Interpreter::normal_table(state), false, false, Rs);
}
void InterpreterMacroAssembler::dispatch_next(TosState state, int step, bool generate_poll) {

6
src/hotspot/cpu/riscv/macroAssembler_riscv.cpp

@ -1125,9 +1125,9 @@ void MacroAssembler::push_CPU_state(bool save_vectors, int vector_size_in_bytes)
// vector registers
if (save_vectors) {
sub(sp, sp, vector_size_in_bytes * VectorRegisterImpl::number_of_registers);
sub(sp, sp, vector_size_in_bytes * VectorRegister::number_of_registers);
vsetvli(t0, x0, Assembler::e64, Assembler::m8);
for (int i = 0; i < VectorRegisterImpl::number_of_registers; i += 8) {
for (int i = 0; i < VectorRegister::number_of_registers; i += 8) {
add(t0, sp, vector_size_in_bytes * i);
vse64_v(as_VectorRegister(i), t0);
}
@ -1139,7 +1139,7 @@ void MacroAssembler::pop_CPU_state(bool restore_vectors, int vector_size_in_byte
// vector registers
if (restore_vectors) {
vsetvli(t0, x0, Assembler::e64, Assembler::m8);
for (int i = 0; i < VectorRegisterImpl::number_of_registers; i += 8) {
for (int i = 0; i < VectorRegister::number_of_registers; i += 8) {
vle64_v(as_VectorRegister(i), sp);
add(sp, sp, vector_size_in_bytes * 8);
}

2
src/hotspot/cpu/riscv/registerMap_riscv.cpp

@ -31,7 +31,7 @@ address RegisterMap::pd_location(VMReg base_reg, int slot_idx) const {
if (base_reg->is_VectorRegister()) {
assert(base_reg->is_concrete(), "must pass base reg");
int base_reg_enc = (base_reg->value() - ConcreteRegisterImpl::max_fpr) /
VectorRegisterImpl::max_slots_per_register;
VectorRegister::max_slots_per_register;
intptr_t offset_in_bytes = slot_idx * VMRegImpl::stack_slot_size;
address base_location = location(base_reg, nullptr);
if (base_location != NULL) {

24
src/hotspot/cpu/riscv/register_riscv.cpp

@ -26,23 +26,11 @@
#include "precompiled.hpp"
#include "register_riscv.hpp"
REGISTER_IMPL_DEFINITION(Register, RegisterImpl, RegisterImpl::number_of_registers);
REGISTER_IMPL_DEFINITION(FloatRegister, FloatRegisterImpl, FloatRegisterImpl::number_of_registers);
REGISTER_IMPL_DEFINITION(VectorRegister, VectorRegisterImpl, VectorRegisterImpl::number_of_registers);
Register::RegisterImpl all_RegisterImpls [Register::number_of_registers + 1];
FloatRegister::FloatRegisterImpl all_FloatRegisterImpls [FloatRegister::number_of_registers + 1];
VectorRegister::VectorRegisterImpl all_VectorRegisterImpls[VectorRegister::number_of_registers + 1];
const int ConcreteRegisterImpl::max_gpr = RegisterImpl::number_of_registers *
RegisterImpl::max_slots_per_register;
const int ConcreteRegisterImpl::max_fpr =
ConcreteRegisterImpl::max_gpr +
FloatRegisterImpl::number_of_registers * FloatRegisterImpl::max_slots_per_register;
const int ConcreteRegisterImpl::max_vpr =
ConcreteRegisterImpl::max_fpr +
VectorRegisterImpl::number_of_registers * VectorRegisterImpl::max_slots_per_register;
const char* RegisterImpl::name() const {
const char* Register::RegisterImpl::name() const {
static const char *const names[number_of_registers] = {
"zr", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "x9",
"c_rarg0", "c_rarg1", "c_rarg2", "c_rarg3", "c_rarg4", "c_rarg5", "c_rarg6", "c_rarg7",
@ -52,7 +40,7 @@ const char* RegisterImpl::name() const {
return is_valid() ? names[encoding()] : "noreg";
}
const char* FloatRegisterImpl::name() const {
const char* FloatRegister::FloatRegisterImpl::name() const {
static const char *const names[number_of_registers] = {
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
@ -62,7 +50,7 @@ const char* FloatRegisterImpl::name() const {
return is_valid() ? names[encoding()] : "noreg";
}
const char* VectorRegisterImpl::name() const {
const char* VectorRegister::VectorRegisterImpl::name() const {
static const char *const names[number_of_registers] = {
"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",

484
src/hotspot/cpu/riscv/register_riscv.hpp

@ -27,6 +27,7 @@
#define CPU_RISCV_REGISTER_RISCV_HPP
#include "asm/register.hpp"
#include "utilities/powerOfTwo.hpp"
#define CSR_FFLAGS 0x001 // Floating-Point Accrued Exceptions.
#define CSR_FRM 0x002 // Floating-Point Dynamic Rounding Mode.
@ -45,14 +46,11 @@
class VMRegImpl;
typedef VMRegImpl* VMReg;
// Use Register as shortcut
class RegisterImpl;
typedef const RegisterImpl* Register;
class Register {
private:
int _encoding;
inline constexpr Register as_Register(int encoding);
class RegisterImpl: public AbstractRegisterImpl {
static constexpr Register first();
constexpr explicit Register(int encoding) : _encoding(encoding) {}
public:
enum {
@ -65,86 +63,114 @@ class RegisterImpl: public AbstractRegisterImpl {
compressed_register_top = 15,
};
// derived registers, offsets, and addresses
const Register successor() const { return this + 1; }
class RegisterImpl: public AbstractRegisterImpl {
friend class Register;
static constexpr const RegisterImpl* first();
public:
// accessors
int raw_encoding() const { return this - first(); }
int encoding() const { assert(is_valid(), "invalid register"); return raw_encoding(); }
bool is_valid() const { return 0 <= raw_encoding() && raw_encoding() < number_of_registers; }
// for rvc
int compressed_raw_encoding() const {
return raw_encoding() - compressed_register_base;
}
int compressed_encoding() const {
assert(is_compressed_valid(), "invalid compressed register");
return encoding() - compressed_register_base;
}
bool is_compressed_valid() const {
return raw_encoding() >= compressed_register_base &&
raw_encoding() <= compressed_register_top;
}
// derived registers, offsets, and addresses
inline Register successor() const;
VMReg as_VMReg() const;
const char* name() const;
};
// construction
inline friend constexpr Register as_Register(int encoding);
VMReg as_VMReg() const;
constexpr Register() : _encoding(-1) {} // noreg
// accessors
int encoding() const { assert(is_valid(), "invalid register"); return encoding_nocheck(); }
int encoding_nocheck() const { return this - first(); }
bool is_valid() const { return (unsigned)encoding_nocheck() < number_of_registers; }
const char* name() const;
int operator==(const Register r) const { return _encoding == r._encoding; }
int operator!=(const Register r) const { return _encoding != r._encoding; }
// for rvc
int compressed_encoding() const {
assert(is_compressed_valid(), "invalid compressed register");
return encoding() - compressed_register_base;
}
int compressed_encoding_nocheck() const {
return encoding_nocheck() - compressed_register_base;
}
bool is_compressed_valid() const {
return encoding_nocheck() >= compressed_register_base &&
encoding_nocheck() <= compressed_register_top;
}
const RegisterImpl* operator->() const { return RegisterImpl::first() + _encoding; }
};
REGISTER_IMPL_DECLARATION(Register, RegisterImpl, RegisterImpl::number_of_registers);
extern Register::RegisterImpl all_RegisterImpls[Register::number_of_registers + 1] INTERNAL_VISIBILITY;
// The integer registers of the RISCV architecture
inline constexpr const Register::RegisterImpl* Register::RegisterImpl::first() {
return all_RegisterImpls + 1;
}
CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1));
constexpr Register noreg = Register();
CONSTANT_REGISTER_DECLARATION(Register, x0, (0));
CONSTANT_REGISTER_DECLARATION(Register, x1, (1));
CONSTANT_REGISTER_DECLARATION(Register, x2, (2));
CONSTANT_REGISTER_DECLARATION(Register, x3, (3));
CONSTANT_REGISTER_DECLARATION(Register, x4, (4));
CONSTANT_REGISTER_DECLARATION(Register, x5, (5));
CONSTANT_REGISTER_DECLARATION(Register, x6, (6));
CONSTANT_REGISTER_DECLARATION(Register, x7, (7));
CONSTANT_REGISTER_DECLARATION(Register, x8, (8));
CONSTANT_REGISTER_DECLARATION(Register, x9, (9));
CONSTANT_REGISTER_DECLARATION(Register, x10, (10));
CONSTANT_REGISTER_DECLARATION(Register, x11, (11));
CONSTANT_REGISTER_DECLARATION(Register, x12, (12));
CONSTANT_REGISTER_DECLARATION(Register, x13, (13));
CONSTANT_REGISTER_DECLARATION(Register, x14, (14));
CONSTANT_REGISTER_DECLARATION(Register, x15, (15));
CONSTANT_REGISTER_DECLARATION(Register, x16, (16));
CONSTANT_REGISTER_DECLARATION(Register, x17, (17));
CONSTANT_REGISTER_DECLARATION(Register, x18, (18));
CONSTANT_REGISTER_DECLARATION(Register, x19, (19));
CONSTANT_REGISTER_DECLARATION(Register, x20, (20));
CONSTANT_REGISTER_DECLARATION(Register, x21, (21));
CONSTANT_REGISTER_DECLARATION(Register, x22, (22));
CONSTANT_REGISTER_DECLARATION(Register, x23, (23));
CONSTANT_REGISTER_DECLARATION(Register, x24, (24));
CONSTANT_REGISTER_DECLARATION(Register, x25, (25));
CONSTANT_REGISTER_DECLARATION(Register, x26, (26));
CONSTANT_REGISTER_DECLARATION(Register, x27, (27));
CONSTANT_REGISTER_DECLARATION(Register, x28, (28));
CONSTANT_REGISTER_DECLARATION(Register, x29, (29));
CONSTANT_REGISTER_DECLARATION(Register, x30, (30));
CONSTANT_REGISTER_DECLARATION(Register, x31, (31));
inline constexpr Register as_Register(int encoding) {
if (0 <= encoding && encoding < Register::number_of_registers) {
return Register(encoding);
}
return noreg;
}
// Use FloatRegister as shortcut
class FloatRegisterImpl;
typedef const FloatRegisterImpl* FloatRegister;
inline Register Register::RegisterImpl::successor() const {
assert(is_valid(), "sanity");
return as_Register(encoding() + 1);
}
inline constexpr FloatRegister as_FloatRegister(int encoding);
// The integer registers of RISCV architecture
constexpr Register x0 = as_Register( 0);
constexpr Register x1 = as_Register( 1);
constexpr Register x2 = as_Register( 2);
constexpr Register x3 = as_Register( 3);
constexpr Register x4 = as_Register( 4);
constexpr Register x5 = as_Register( 5);
constexpr Register x6 = as_Register( 6);
constexpr Register x7 = as_Register( 7);
constexpr Register x8 = as_Register( 8);
constexpr Register x9 = as_Register( 9);
constexpr Register x10 = as_Register(10);
constexpr Register x11 = as_Register(11);
constexpr Register x12 = as_Register(12);
constexpr Register x13 = as_Register(13);
constexpr Register x14 = as_Register(14);
constexpr Register x15 = as_Register(15);
constexpr Register x16 = as_Register(16);
constexpr Register x17 = as_Register(17);
constexpr Register x18 = as_Register(18);
constexpr Register x19 = as_Register(19);
constexpr Register x20 = as_Register(20);
constexpr Register x21 = as_Register(21);
constexpr Register x22 = as_Register(22);
constexpr Register x23 = as_Register(23);
constexpr Register x24 = as_Register(24);
constexpr Register x25 = as_Register(25);
constexpr Register x26 = as_Register(26);
constexpr Register x27 = as_Register(27);
constexpr Register x28 = as_Register(28);
constexpr Register x29 = as_Register(29);
constexpr Register x30 = as_Register(30);
constexpr Register x31 = as_Register(31);
// The implementation of floating point registers for the architecture
class FloatRegisterImpl: public AbstractRegisterImpl {
static constexpr FloatRegister first();
class FloatRegister {
private:
int _encoding;
constexpr explicit FloatRegister(int encoding) : _encoding(encoding) {}
public:
inline friend constexpr FloatRegister as_FloatRegister(int encoding);
enum {
number_of_registers = 32,
max_slots_per_register = 2,
@ -154,171 +180,235 @@ class FloatRegisterImpl: public AbstractRegisterImpl {
compressed_register_top = 15,
};
// construction
inline friend constexpr FloatRegister as_FloatRegister(int encoding);
class FloatRegisterImpl: public AbstractRegisterImpl {
friend class FloatRegister;
VMReg as_VMReg() const;
static constexpr const FloatRegisterImpl* first();
// derived registers, offsets, and addresses
FloatRegister successor() const {
return as_FloatRegister((encoding() + 1) % (unsigned)number_of_registers);
}
public:
// accessors
int raw_encoding() const { return this - first(); }
int encoding() const { assert(is_valid(), "invalid register"); return raw_encoding(); }
bool is_valid() const { return 0 <= raw_encoding() && raw_encoding() < number_of_registers; }
// accessors
int encoding() const { assert(is_valid(), "invalid register"); return encoding_nocheck(); }
int encoding_nocheck() const { return this - first(); }
int is_valid() const { return (unsigned)encoding_nocheck() < number_of_registers; }
const char* name() const;
// for rvc
int compressed_raw_encoding() const {
return raw_encoding() - compressed_register_base;
}
// for rvc
int compressed_encoding() const {
assert(is_compressed_valid(), "invalid compressed register");
return encoding() - compressed_register_base;
}
int compressed_encoding() const {
assert(is_compressed_valid(), "invalid compressed register");
return encoding() - compressed_register_base;
}
int compressed_encoding_nocheck() const {
return encoding_nocheck() - compressed_register_base;
}
bool is_compressed_valid() const {
return raw_encoding() >= compressed_register_base &&
raw_encoding() <= compressed_register_top;
}
bool is_compressed_valid() const {
return encoding_nocheck() >= compressed_register_base &&
encoding_nocheck() <= compressed_register_top;
}
// derived registers, offsets, and addresses
inline FloatRegister successor() const;
VMReg as_VMReg() const;
const char* name() const;
};
constexpr FloatRegister() : _encoding(-1) {} // fnoreg
int operator==(const FloatRegister r) const { return _encoding == r._encoding; }
int operator!=(const FloatRegister r) const { return _encoding != r._encoding; }
const FloatRegisterImpl* operator->() const { return FloatRegisterImpl::first() + _encoding; }
};
REGISTER_IMPL_DECLARATION(FloatRegister, FloatRegisterImpl, FloatRegisterImpl::number_of_registers);
extern FloatRegister::FloatRegisterImpl all_FloatRegisterImpls[FloatRegister::number_of_registers + 1] INTERNAL_VISIBILITY;
inline constexpr const FloatRegister::FloatRegisterImpl* FloatRegister::FloatRegisterImpl::first() {
return all_FloatRegisterImpls + 1;
}
constexpr FloatRegister fnoreg = FloatRegister();
inline constexpr FloatRegister as_FloatRegister(int encoding) {
if (0 <= encoding && encoding < FloatRegister::number_of_registers) {
return FloatRegister(encoding);
}
return fnoreg;
}
inline FloatRegister FloatRegister::FloatRegisterImpl::successor() const {
assert(is_valid(), "sanity");
return as_FloatRegister(encoding() + 1);
}
// The float registers of the RISCV architecture
CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg , (-1));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f0 , ( 0));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f1 , ( 1));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f2 , ( 2));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f3 , ( 3));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f4 , ( 4));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f5 , ( 5));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f6 , ( 6));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f7 , ( 7));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f8 , ( 8));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f9 , ( 9));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f10 , (10));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f11 , (11));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f12 , (12));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f13 , (13));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f14 , (14));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f15 , (15));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f16 , (16));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f17 , (17));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f18 , (18));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f19 , (19));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f20 , (20));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f21 , (21));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f22 , (22));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f23 , (23));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f24 , (24));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f25 , (25));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f26 , (26));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f27 , (27));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f28 , (28));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f29 , (29));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f30 , (30));
CONSTANT_REGISTER_DECLARATION(FloatRegister, f31 , (31));
// Use VectorRegister as shortcut
class VectorRegisterImpl;
typedef const VectorRegisterImpl* VectorRegister;
inline constexpr VectorRegister as_VectorRegister(int encoding);
constexpr FloatRegister f0 = as_FloatRegister( 0);
constexpr FloatRegister f1 = as_FloatRegister( 1);
constexpr FloatRegister f2 = as_FloatRegister( 2);
constexpr FloatRegister f3 = as_FloatRegister( 3);
constexpr FloatRegister f4 = as_FloatRegister( 4);
constexpr FloatRegister f5 = as_FloatRegister( 5);
constexpr FloatRegister f6 = as_FloatRegister( 6);
constexpr FloatRegister f7 = as_FloatRegister( 7);
constexpr FloatRegister f8 = as_FloatRegister( 8);
constexpr FloatRegister f9 = as_FloatRegister( 9);
constexpr FloatRegister f10 = as_FloatRegister(10);
constexpr FloatRegister f11 = as_FloatRegister(11);
constexpr FloatRegister f12 = as_FloatRegister(12);
constexpr FloatRegister f13 = as_FloatRegister(13);
constexpr FloatRegister f14 = as_FloatRegister(14);
constexpr FloatRegister f15 = as_FloatRegister(15);
constexpr FloatRegister f16 = as_FloatRegister(16);
constexpr FloatRegister f17 = as_FloatRegister(17);
constexpr FloatRegister f18 = as_FloatRegister(18);
constexpr FloatRegister f19 = as_FloatRegister(19);
constexpr FloatRegister f20 = as_FloatRegister(20);
constexpr FloatRegister f21 = as_FloatRegister(21);
constexpr FloatRegister f22 = as_FloatRegister(22);
constexpr FloatRegister f23 = as_FloatRegister(23);
constexpr FloatRegister f24 = as_FloatRegister(24);
constexpr FloatRegister f25 = as_FloatRegister(25);
constexpr FloatRegister f26 = as_FloatRegister(26);
constexpr FloatRegister f27 = as_FloatRegister(27);
constexpr FloatRegister f28 = as_FloatRegister(28);
constexpr FloatRegister f29 = as_FloatRegister(29);
constexpr FloatRegister f30 = as_FloatRegister(30);
constexpr FloatRegister f31 = as_FloatRegister(31);
// The implementation of vector registers for RVV
class VectorRegisterImpl: public AbstractRegisterImpl {
static constexpr VectorRegister first();
class VectorRegister {
int _encoding;
constexpr explicit VectorRegister(int encoding) : _encoding(encoding) {}
public:
inline friend constexpr VectorRegister as_VectorRegister(int encoding);
enum {
number_of_registers = 32,
max_slots_per_register = 4
};
// construction
inline friend constexpr VectorRegister as_VectorRegister(int encoding);
class VectorRegisterImpl: public AbstractRegisterImpl {
friend class VectorRegister;
VMReg as_VMReg() const;
static constexpr const VectorRegisterImpl* first();
// derived registers, offsets, and addresses
VectorRegister successor() const { return this + 1; }
public:
// accessors
int raw_encoding() const { return this - first(); }
int encoding() const { assert(is_valid(), "invalid register"); return raw_encoding(); }
bool is_valid() const { return 0 <= raw_encoding() && raw_encoding() < number_of_registers; }
// accessors
int encoding() const { assert(is_valid(), "invalid register"); return encoding_nocheck(); }
int encoding_nocheck() const { return this - first(); }
bool is_valid() const { return (unsigned)encoding_nocheck() < number_of_registers; }
const char* name() const;
// derived registers, offsets, and addresses
inline VectorRegister successor() const;
VMReg as_VMReg() const;
const char* name() const;
};
constexpr VectorRegister() : _encoding(-1) {} // vnoreg
int operator==(const VectorRegister r) const { return _encoding == r._encoding; }
int operator!=(const VectorRegister r) const { return _encoding != r._encoding; }
const VectorRegisterImpl* operator->() const { return VectorRegisterImpl::first() + _encoding; }
};
REGISTER_IMPL_DECLARATION(VectorRegister, VectorRegisterImpl, VectorRegisterImpl::number_of_registers);
extern VectorRegister::VectorRegisterImpl all_VectorRegisterImpls[VectorRegister::number_of_registers + 1] INTERNAL_VISIBILITY;
inline constexpr const VectorRegister::VectorRegisterImpl* VectorRegister::VectorRegisterImpl::first() {
return all_VectorRegisterImpls + 1;
}
constexpr VectorRegister vnoreg = VectorRegister();
inline constexpr VectorRegister as_VectorRegister(int encoding) {
if (0 <= encoding && encoding < VectorRegister::number_of_registers) {
return VectorRegister(encoding);
}
return vnoreg;
}
inline VectorRegister VectorRegister::VectorRegisterImpl::successor() const {
assert(is_valid(), "sanity");
return as_VectorRegister(encoding() + 1);
}
// The vector registers of RVV
CONSTANT_REGISTER_DECLARATION(VectorRegister, vnoreg , (-1));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v0 , ( 0));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v1 , ( 1));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v2 , ( 2));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v3 , ( 3));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v4 , ( 4));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v5 , ( 5));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v6 , ( 6));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v7 , ( 7));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v8 , ( 8));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v9 , ( 9));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v10 , (10));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v11 , (11));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v12 , (12));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v13 , (13));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v14 , (14));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v15 , (15));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v16 , (16));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v17 , (17));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v18 , (18));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v19 , (19));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v20 , (20));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v21 , (21));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v22 , (22));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v23 , (23));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v24 , (24));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v25 , (25));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v26 , (26));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v27 , (27));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v28 , (28));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v29 , (29));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v30 , (30));
CONSTANT_REGISTER_DECLARATION(VectorRegister, v31 , (31));
constexpr VectorRegister v0 = as_VectorRegister( 0);
constexpr VectorRegister v1 = as_VectorRegister( 1);
constexpr VectorRegister v2 = as_VectorRegister( 2);
constexpr VectorRegister v3 = as_VectorRegister( 3);
constexpr VectorRegister v4 = as_VectorRegister( 4);
constexpr VectorRegister v5 = as_VectorRegister( 5);
constexpr VectorRegister v6 = as_VectorRegister( 6);
constexpr VectorRegister v7 = as_VectorRegister( 7);
constexpr VectorRegister v8 = as_VectorRegister( 8);
constexpr VectorRegister v9 = as_VectorRegister( 9);
constexpr VectorRegister v10 = as_VectorRegister(10);
constexpr VectorRegister v11 = as_VectorRegister(11);
constexpr VectorRegister v12 = as_VectorRegister(12);
constexpr VectorRegister v13 = as_VectorRegister(13);
constexpr VectorRegister v14 = as_VectorRegister(14);
constexpr VectorRegister v15 = as_VectorRegister(15);
constexpr VectorRegister v16 = as_VectorRegister(16);
constexpr VectorRegister v17 = as_VectorRegister(17);
constexpr VectorRegister v18 = as_VectorRegister(18);
constexpr VectorRegister v19 = as_VectorRegister(19);
constexpr VectorRegister v20 = as_VectorRegister(20);
constexpr VectorRegister v21 = as_VectorRegister(21);
constexpr VectorRegister v22 = as_VectorRegister(22);
constexpr VectorRegister v23 = as_VectorRegister(23);
constexpr VectorRegister v24 = as_VectorRegister(24);
constexpr VectorRegister v25 = as_VectorRegister(25);
constexpr VectorRegister v26 = as_VectorRegister(26);
constexpr VectorRegister v27 = as_VectorRegister(27);
constexpr VectorRegister v28 = as_VectorRegister(28);
constexpr VectorRegister v29 = as_VectorRegister(29);
constexpr VectorRegister v30 = as_VectorRegister(30);
constexpr VectorRegister v31 = as_VectorRegister(31);
// Need to know the total number of registers of all sorts for SharedInfo.
// Define a class that exports it.
class ConcreteRegisterImpl : public AbstractRegisterImpl {
public:
enum {
// A big enough number for C2: all the registers plus flags
// This number must be large enough to cover REG_COUNT (defined by c2) registers.
// There is no requirement that any ordering here matches any ordering c2 gives
// it's optoregs.
max_gpr = Register::number_of_registers * Register::max_slots_per_register,
max_fpr = max_gpr + FloatRegister::number_of_registers * FloatRegister::max_slots_per_register,
max_vpr = max_fpr + VectorRegister::number_of_registers * VectorRegister::max_slots_per_register,
number_of_registers = (RegisterImpl::max_slots_per_register * RegisterImpl::number_of_registers +
FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers +
VectorRegisterImpl::max_slots_per_register * VectorRegisterImpl::number_of_registers)
// A big enough number for C2: all the registers plus flags
// This number must be large enough to cover REG_COUNT (defined by c2) registers.
// There is no requirement that any ordering here matches any ordering c2 gives
// it's optoregs.
number_of_registers = max_vpr // gpr/fpr/vpr
};
// added to make it compile
static const int max_gpr;
static const int max_fpr;
static const int max_vpr;
};
typedef AbstractRegSet<Register> RegSet;
typedef AbstractRegSet<FloatRegister> FloatRegSet;
typedef AbstractRegSet<VectorRegister> VectorRegSet;
template <>
inline Register AbstractRegSet<Register>::first() {
uint32_t first = _bitset & -_bitset;
return first ? as_Register(exact_log2(first)) : noreg;
}
template <>
inline FloatRegister AbstractRegSet<FloatRegister>::first() {
uint32_t first = _bitset & -_bitset;
return first ? as_FloatRegister(exact_log2(first)) : fnoreg;
}
template<>
inline VectorRegister AbstractRegSet<VectorRegister>::first() {
uint32_t first = _bitset & -_bitset;
return first ? as_VectorRegister(exact_log2(first)) : vnoreg;
}
#endif // CPU_RISCV_REGISTER_RISCV_HPP

6
src/hotspot/cpu/riscv/riscv.ad

@ -1469,19 +1469,19 @@ static enum RC rc_class(OptoReg::Name reg) {
// we have 30 int registers * 2 halves
// (t0 and t1 are omitted)
int slots_of_int_registers = RegisterImpl::max_slots_per_register * (RegisterImpl::number_of_registers - 2);
int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
if (reg < slots_of_int_registers) {
return rc_int;
}
// we have 32 float register * 2 halves
int slots_of_float_registers = FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers;
int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
if (reg < slots_of_int_registers + slots_of_float_registers) {
return rc_float;
}
// we have 32 vector register * 4 halves
int slots_of_vector_registers = VectorRegisterImpl::max_slots_per_register * VectorRegisterImpl::number_of_registers;
int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
return rc_vector;
}

34
src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp

@ -111,7 +111,7 @@ class RegisterSaver {
int f0_offset = 0;
#ifdef COMPILER2
if (_save_vectors) {
f0_offset += Matcher::scalable_vector_reg_size(T_INT) * VectorRegisterImpl::number_of_registers *
f0_offset += Matcher::scalable_vector_reg_size(T_INT) * VectorRegister::number_of_registers *
BytesPerInt;
}
#endif
@ -119,8 +119,8 @@ class RegisterSaver {
}
int reserved_slot_offset_in_bytes(void) {
return f0_offset_in_bytes() +
FloatRegisterImpl::max_slots_per_register *
FloatRegisterImpl::number_of_registers *
FloatRegister::max_slots_per_register *
FloatRegister::number_of_registers *
BytesPerInt;
}
@ -135,8 +135,8 @@ class RegisterSaver {
int ra_offset_in_bytes(void) {
return reserved_slot_offset_in_bytes() +
(RegisterImpl::number_of_registers - 3) *
RegisterImpl::max_slots_per_register *
(Register::number_of_registers - 3) *
Register::max_slots_per_register *
BytesPerInt;
}
};
@ -178,24 +178,24 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_
int step_in_slots = 0;
if (_save_vectors) {
step_in_slots = vector_size_in_slots;
for (int i = 0; i < VectorRegisterImpl::number_of_registers; i++, sp_offset_in_slots += step_in_slots) {
for (int i = 0; i < VectorRegister::number_of_registers; i++, sp_offset_in_slots += step_in_slots) {
VectorRegister r = as_VectorRegister(i);
oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset_in_slots), r->as_VMReg());
}
}
step_in_slots = FloatRegisterImpl::max_slots_per_register;
for (int i = 0; i < FloatRegisterImpl::number_of_registers; i++, sp_offset_in_slots += step_in_slots) {
step_in_slots = FloatRegister::max_slots_per_register;
for (int i = 0; i < FloatRegister::number_of_registers; i++, sp_offset_in_slots += step_in_slots) {
FloatRegister r = as_FloatRegister(i);
oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset_in_slots), r->as_VMReg());
}
step_in_slots = RegisterImpl::max_slots_per_register;
step_in_slots = Register::max_slots_per_register;
// skip the slot reserved for alignment, see MacroAssembler::push_reg;
// also skip x5 ~ x6 on the stack because they are caller-saved registers.
sp_offset_in_slots += RegisterImpl::max_slots_per_register * 3;
sp_offset_in_slots += Register::max_slots_per_register * 3;
// besides, we ignore x0 ~ x4 because push_CPU_state won't push them on the stack.
for (int i = 7; i < RegisterImpl::number_of_registers; i++, sp_offset_in_slots += step_in_slots) {
for (int i = 7; i < Register::number_of_registers; i++, sp_offset_in_slots += step_in_slots) {
Register r = as_Register(i);
if (r != xthread) {
oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset_in_slots + additional_frame_slots), r->as_VMReg());
@ -242,8 +242,8 @@ static int reg2offset_out(VMReg r) {
// refer to 4-byte stack slots. All stack slots are based off of the stack pointer
// as framesizes are fixed.
// VMRegImpl::stack0 refers to the first slot 0(sp).
// and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
// up to RegisterImpl::number_of_registers) are the 64-bit
// and VMRegImpl::stack0+1 refers to the memory word 4-byes higher.
// Register up to Register::number_of_registers) are the 64-bit
// integer registers.
// Note: the INPUTS in sig_bt are in units of Java argument words,
@ -1368,12 +1368,12 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
int int_args = 0;
#ifdef ASSERT
bool reg_destroyed[RegisterImpl::number_of_registers];
bool freg_destroyed[FloatRegisterImpl::number_of_registers];
for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
bool reg_destroyed[Register::number_of_registers];
bool freg_destroyed[FloatRegister::number_of_registers];
for ( int r = 0 ; r < Register::number_of_registers ; r++ ) {
reg_destroyed[r] = false;
}
for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
for ( int f = 0 ; f < FloatRegister::number_of_registers ; f++ ) {
freg_destroyed[f] = false;
}

41
src/hotspot/cpu/riscv/stubGenerator_riscv.cpp

@ -2946,32 +2946,32 @@ class StubGenerator: public StubCodeGenerator {
// Register allocation
Register reg = c_rarg0;
Pa_base = reg; // Argument registers
RegSetIterator<Register> regs = RegSet::range(x10, x26).begin();
Pa_base = *regs; // Argument registers
if (squaring) {
Pb_base = Pa_base;
} else {
Pb_base = ++reg;
Pb_base = *++regs;
}
Pn_base = ++reg;
Rlen= ++reg;
inv = ++reg;
Pm_base = ++reg;
Pn_base = *++regs;
Rlen= *++regs;
inv = *++regs;
Pm_base = *++regs;
// Working registers:
Ra = ++reg; // The current digit of a, b, n, and m.
Rb = ++reg;
Rm = ++reg;
Rn = ++reg;
Ra = *++regs; // The current digit of a, b, n, and m.
Rb = *++regs;
Rm = *++regs;
Rn = *++regs;
Pa = ++reg; // Pointers to the current/next digit of a, b, n, and m.
Pb = ++reg;
Pm = ++reg;
Pn = ++reg;
Pa = *++regs; // Pointers to the current/next digit of a, b, n, and m.
Pb = *++regs;
Pm = *++regs;
Pn = *++regs;
tmp0 = ++reg; // Three registers which form a
tmp1 = ++reg; // triple-precision accumuator.
tmp2 = ++reg;
tmp0 = *++regs; // Three registers which form a
tmp1 = *++regs; // triple-precision accumuator.
tmp2 = *++regs;
Ri = x6; // Inner and outer loop indexes.
Rj = x7;
@ -2982,7 +2982,7 @@ class StubGenerator: public StubCodeGenerator {
Rlo_mn = x31;
// x18 and up are callee-saved.
_toSave = RegSet::range(x18, reg) + Pm_base;
_toSave = RegSet::range(x18, *regs) + Pm_base;
}
private:
@ -3238,7 +3238,8 @@ class StubGenerator: public StubCodeGenerator {
// Preserves len
// Leaves s pointing to the address which was in d at start
void reverse(Register d, Register s, Register len, Register tmp1, Register tmp2) {
assert(tmp1 < x28 && tmp2 < x28, "register corruption");
assert(tmp1->encoding() < x28->encoding(), "register corruption");
assert(tmp2->encoding() < x28->encoding(), "register corruption");
slli(tmp1, len, LogBytesPerWord);
add(s, s, tmp1);

6
src/hotspot/cpu/riscv/vmreg_riscv.cpp

@ -31,7 +31,7 @@ void VMRegImpl::set_regName() {
int i = 0;
Register reg = ::as_Register(0);
for ( ; i < ConcreteRegisterImpl::max_gpr ; ) {
for (int j = 0 ; j < RegisterImpl::max_slots_per_register ; j++) {
for (int j = 0 ; j < Register::max_slots_per_register ; j++) {
regName[i++] = reg->name();
}
reg = reg->successor();
@ -39,7 +39,7 @@ void VMRegImpl::set_regName() {
FloatRegister freg = ::as_FloatRegister(0);
for ( ; i < ConcreteRegisterImpl::max_fpr ; ) {
for (int j = 0 ; j < FloatRegisterImpl::max_slots_per_register ; j++) {
for (int j = 0 ; j < FloatRegister::max_slots_per_register ; j++) {
regName[i++] = reg->name();
}
freg = freg->successor();
@ -47,7 +47,7 @@ void VMRegImpl::set_regName() {
VectorRegister vreg = ::as_VectorRegister(0);
for ( ; i < ConcreteRegisterImpl::max_vpr ; ) {
for (int j = 0 ; j < VectorRegisterImpl::max_slots_per_register ; j++) {
for (int j = 0 ; j < VectorRegister::max_slots_per_register ; j++) {
regName[i++] = reg->name();
}
vreg = vreg->successor();

10
src/hotspot/cpu/riscv/vmreg_riscv.hpp

@ -40,26 +40,26 @@ inline bool is_VectorRegister() {
inline Register as_Register() {
assert(is_Register(), "must be");
return ::as_Register(value() / RegisterImpl::max_slots_per_register);
return ::as_Register(value() / Register::max_slots_per_register);
}
inline FloatRegister as_FloatRegister() {
assert(is_FloatRegister() && is_even(value()), "must be");
return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) /
FloatRegisterImpl::max_slots_per_register);
FloatRegister::max_slots_per_register);
}
inline VectorRegister as_VectorRegister() {
assert(is_VectorRegister() && ((value() & (VectorRegisterImpl::max_slots_per_register - 1)) == 0), "must be");
assert(is_VectorRegister() && ((value() & (VectorRegister::max_slots_per_register - 1)) == 0), "must be");
return ::as_VectorRegister((value() - ConcreteRegisterImpl::max_fpr) /
VectorRegisterImpl::max_slots_per_register);
VectorRegister::max_slots_per_register);
}
inline bool is_concrete() {
assert(is_reg(), "must be");
if (is_VectorRegister()) {
int base = value() - ConcreteRegisterImpl::max_fpr;
return (base % VectorRegisterImpl::max_slots_per_register) == 0;
return (base % VectorRegister::max_slots_per_register) == 0;
} else {
return is_even(value());
}

15
src/hotspot/cpu/riscv/vmreg_riscv.inline.hpp

@ -26,20 +26,17 @@
#ifndef CPU_RISCV_VM_VMREG_RISCV_INLINE_HPP
#define CPU_RISCV_VM_VMREG_RISCV_INLINE_HPP
inline VMReg RegisterImpl::as_VMReg() const {
if (this == noreg) {
return VMRegImpl::Bad();
}
return VMRegImpl::as_VMReg(encoding() * RegisterImpl::max_slots_per_register);
inline VMReg Register::RegisterImpl::as_VMReg() const {
return VMRegImpl::as_VMReg(encoding() * Register::max_slots_per_register);
}
inline VMReg FloatRegisterImpl::as_VMReg() const {
return VMRegImpl::as_VMReg((encoding() * FloatRegisterImpl::max_slots_per_register) +
inline VMReg FloatRegister::FloatRegisterImpl::as_VMReg() const {
return VMRegImpl::as_VMReg((encoding() * FloatRegister::max_slots_per_register) +
ConcreteRegisterImpl::max_gpr);
}
inline VMReg VectorRegisterImpl::as_VMReg() const {
return VMRegImpl::as_VMReg((encoding() * VectorRegisterImpl::max_slots_per_register) +
inline VMReg VectorRegister::VectorRegisterImpl::as_VMReg() const {
return VMRegImpl::as_VMReg((encoding() * VectorRegister::max_slots_per_register) +
ConcreteRegisterImpl::max_fpr);
}