8215547: ZGC: Fix incorrect match rule for loadBarrierWeakSlowRegNoVec
Reviewed-by: eosterlund, neliasso
This commit is contained in:
parent
83adde9866
commit
2778c86488
src/hotspot
@ -4265,132 +4265,196 @@ operand cmpOpUCF2() %{
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// Operands for bound floating pointer register arguments
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// Operands for bound floating pointer register arguments
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operand rxmm0() %{
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operand rxmm0() %{
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constraint(ALLOC_IN_RC(xmm0_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm0_reg));
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predicate((UseSSE > 0) && (UseAVX<= 2)); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm1() %{
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operand rxmm1() %{
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constraint(ALLOC_IN_RC(xmm1_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm1_reg));
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predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm2() %{
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operand rxmm2() %{
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constraint(ALLOC_IN_RC(xmm2_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm2_reg));
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predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm3() %{
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operand rxmm3() %{
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constraint(ALLOC_IN_RC(xmm3_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm3_reg));
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predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm4() %{
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operand rxmm4() %{
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constraint(ALLOC_IN_RC(xmm4_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm4_reg));
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predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm5() %{
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operand rxmm5() %{
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constraint(ALLOC_IN_RC(xmm5_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm5_reg));
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predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm6() %{
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operand rxmm6() %{
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constraint(ALLOC_IN_RC(xmm6_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm6_reg));
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predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm7() %{
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operand rxmm7() %{
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constraint(ALLOC_IN_RC(xmm7_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm7_reg));
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predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm8() %{
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operand rxmm8() %{
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constraint(ALLOC_IN_RC(xmm8_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm8_reg));
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predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm9() %{
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operand rxmm9() %{
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constraint(ALLOC_IN_RC(xmm9_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm9_reg));
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predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm10() %{
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operand rxmm10() %{
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constraint(ALLOC_IN_RC(xmm10_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm10_reg));
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predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm11() %{
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operand rxmm11() %{
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constraint(ALLOC_IN_RC(xmm11_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm11_reg));
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predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm12() %{
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operand rxmm12() %{
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constraint(ALLOC_IN_RC(xmm12_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm12_reg));
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predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm13() %{
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operand rxmm13() %{
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constraint(ALLOC_IN_RC(xmm13_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm13_reg));
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predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm14() %{
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operand rxmm14() %{
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constraint(ALLOC_IN_RC(xmm14_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm14_reg));
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predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm15() %{
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operand rxmm15() %{
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constraint(ALLOC_IN_RC(xmm15_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm15_reg));
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predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm16() %{
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operand rxmm16() %{
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constraint(ALLOC_IN_RC(xmm16_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm16_reg));
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predicate(UseAVX == 3); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm17() %{
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operand rxmm17() %{
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constraint(ALLOC_IN_RC(xmm17_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm17_reg));
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predicate(UseAVX == 3); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm18() %{
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operand rxmm18() %{
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constraint(ALLOC_IN_RC(xmm18_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm18_reg));
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predicate(UseAVX == 3); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm19() %{
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operand rxmm19() %{
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constraint(ALLOC_IN_RC(xmm19_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm19_reg));
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predicate(UseAVX == 3); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm20() %{
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operand rxmm20() %{
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constraint(ALLOC_IN_RC(xmm20_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm20_reg));
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predicate(UseAVX == 3); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm21() %{
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operand rxmm21() %{
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constraint(ALLOC_IN_RC(xmm21_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm21_reg));
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predicate(UseAVX == 3); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm22() %{
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operand rxmm22() %{
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constraint(ALLOC_IN_RC(xmm22_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm22_reg));
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predicate(UseAVX == 3); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm23() %{
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operand rxmm23() %{
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constraint(ALLOC_IN_RC(xmm23_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm23_reg));
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predicate(UseAVX == 3); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm24() %{
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operand rxmm24() %{
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constraint(ALLOC_IN_RC(xmm24_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm24_reg));
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predicate(UseAVX == 3); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm25() %{
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operand rxmm25() %{
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constraint(ALLOC_IN_RC(xmm25_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm25_reg));
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predicate(UseAVX == 3); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm26() %{
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operand rxmm26() %{
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constraint(ALLOC_IN_RC(xmm26_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm26_reg));
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predicate(UseAVX == 3); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm27() %{
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operand rxmm27() %{
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constraint(ALLOC_IN_RC(xmm27_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm27_reg));
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predicate(UseAVX == 3); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm28() %{
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operand rxmm28() %{
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constraint(ALLOC_IN_RC(xmm28_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm28_reg));
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predicate(UseAVX == 3); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm29() %{
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operand rxmm29() %{
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constraint(ALLOC_IN_RC(xmm29_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm29_reg));
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predicate(UseAVX == 3); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm30() %{
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operand rxmm30() %{
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constraint(ALLOC_IN_RC(xmm30_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm30_reg));
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predicate(UseAVX == 3); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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operand rxmm31() %{
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operand rxmm31() %{
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constraint(ALLOC_IN_RC(xmm31_reg)); match(VecX);
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constraint(ALLOC_IN_RC(xmm31_reg));
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predicate(UseAVX == 3); format%{%} interface(REG_INTER);
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match(VecX);
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format%{%}
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interface(REG_INTER);
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%}
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%}
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//----------OPERAND CLASSES----------------------------------------------------
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//----------OPERAND CLASSES----------------------------------------------------
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@ -12651,33 +12715,6 @@ instruct RethrowException()
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// Execute ZGC load barrier (strong) slow path
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// Execute ZGC load barrier (strong) slow path
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//
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//
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// When running without XMM regs
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instruct loadBarrierSlowRegNoVec(rRegP dst, memory mem, rFlagsReg cr) %{
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match(Set dst (LoadBarrierSlowReg mem));
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predicate(MaxVectorSize < 16);
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effect(DEF dst, KILL cr);
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format %{"LoadBarrierSlowRegNoVec $dst, $mem" %}
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ins_encode %{
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#if INCLUDE_ZGC
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Register d = $dst$$Register;
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ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
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assert(d != r12, "Can't be R12!");
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assert(d != r15, "Can't be R15!");
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assert(d != rsp, "Can't be RSP!");
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__ lea(d, $mem$$Address);
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__ call(RuntimeAddress(bs->load_barrier_slow_stub(d)));
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#else
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ShouldNotReachHere();
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#endif
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%}
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ins_pipe(pipe_slow);
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%}
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// For XMM and YMM enabled processors
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// For XMM and YMM enabled processors
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instruct loadBarrierSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
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instruct loadBarrierSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
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rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
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rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
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@ -12686,7 +12723,7 @@ instruct loadBarrierSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
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rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
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rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
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match(Set dst (LoadBarrierSlowReg mem));
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match(Set dst (LoadBarrierSlowReg mem));
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predicate((UseSSE > 0) && (UseAVX <= 2) && (MaxVectorSize >= 16));
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predicate(UseAVX <= 2);
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effect(DEF dst, KILL cr,
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effect(DEF dst, KILL cr,
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KILL x0, KILL x1, KILL x2, KILL x3,
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KILL x0, KILL x1, KILL x2, KILL x3,
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@ -12694,7 +12731,7 @@ instruct loadBarrierSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
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KILL x8, KILL x9, KILL x10, KILL x11,
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KILL x8, KILL x9, KILL x10, KILL x11,
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KILL x12, KILL x13, KILL x14, KILL x15);
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KILL x12, KILL x13, KILL x14, KILL x15);
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format %{"LoadBarrierSlowRegXmm $dst, $mem" %}
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format %{"LoadBarrierSlowRegXmmAndYmm $dst, $mem" %}
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ins_encode %{
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ins_encode %{
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#if INCLUDE_ZGC
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#if INCLUDE_ZGC
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Register d = $dst$$Register;
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Register d = $dst$$Register;
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@ -12725,7 +12762,7 @@ instruct loadBarrierSlowRegZmm(rRegP dst, memory mem, rFlagsReg cr,
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rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
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rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
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match(Set dst (LoadBarrierSlowReg mem));
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match(Set dst (LoadBarrierSlowReg mem));
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predicate((UseAVX == 3) && (MaxVectorSize >= 16));
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predicate(UseAVX == 3);
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effect(DEF dst, KILL cr,
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effect(DEF dst, KILL cr,
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KILL x0, KILL x1, KILL x2, KILL x3,
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KILL x0, KILL x1, KILL x2, KILL x3,
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@ -12760,33 +12797,6 @@ instruct loadBarrierSlowRegZmm(rRegP dst, memory mem, rFlagsReg cr,
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// Execute ZGC load barrier (weak) slow path
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// Execute ZGC load barrier (weak) slow path
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//
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//
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// When running without XMM regs
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instruct loadBarrierWeakSlowRegNoVec(rRegP dst, memory mem, rFlagsReg cr) %{
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match(Set dst (LoadBarrierSlowReg mem));
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predicate(MaxVectorSize < 16);
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effect(DEF dst, KILL cr);
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format %{"LoadBarrierSlowRegNoVec $dst, $mem" %}
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ins_encode %{
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#if INCLUDE_ZGC
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Register d = $dst$$Register;
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ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
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assert(d != r12, "Can't be R12!");
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assert(d != r15, "Can't be R15!");
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assert(d != rsp, "Can't be RSP!");
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__ lea(d, $mem$$Address);
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__ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d)));
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#else
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ShouldNotReachHere();
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#endif
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%}
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ins_pipe(pipe_slow);
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%}
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// For XMM and YMM enabled processors
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// For XMM and YMM enabled processors
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instruct loadBarrierWeakSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
|
instruct loadBarrierWeakSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
|
||||||
rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
|
rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
|
||||||
@ -12795,7 +12805,7 @@ instruct loadBarrierWeakSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
|
|||||||
rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
|
rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
|
||||||
|
|
||||||
match(Set dst (LoadBarrierWeakSlowReg mem));
|
match(Set dst (LoadBarrierWeakSlowReg mem));
|
||||||
predicate((UseSSE > 0) && (UseAVX <= 2) && (MaxVectorSize >= 16));
|
predicate(UseAVX <= 2);
|
||||||
|
|
||||||
effect(DEF dst, KILL cr,
|
effect(DEF dst, KILL cr,
|
||||||
KILL x0, KILL x1, KILL x2, KILL x3,
|
KILL x0, KILL x1, KILL x2, KILL x3,
|
||||||
@ -12803,7 +12813,7 @@ instruct loadBarrierWeakSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
|
|||||||
KILL x8, KILL x9, KILL x10, KILL x11,
|
KILL x8, KILL x9, KILL x10, KILL x11,
|
||||||
KILL x12, KILL x13, KILL x14, KILL x15);
|
KILL x12, KILL x13, KILL x14, KILL x15);
|
||||||
|
|
||||||
format %{"LoadBarrierWeakSlowRegXmm $dst, $mem" %}
|
format %{"LoadBarrierWeakSlowRegXmmAndYmm $dst, $mem" %}
|
||||||
ins_encode %{
|
ins_encode %{
|
||||||
#if INCLUDE_ZGC
|
#if INCLUDE_ZGC
|
||||||
Register d = $dst$$Register;
|
Register d = $dst$$Register;
|
||||||
@ -12834,7 +12844,7 @@ instruct loadBarrierWeakSlowRegZmm(rRegP dst, memory mem, rFlagsReg cr,
|
|||||||
rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
|
rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
|
||||||
|
|
||||||
match(Set dst (LoadBarrierWeakSlowReg mem));
|
match(Set dst (LoadBarrierWeakSlowReg mem));
|
||||||
predicate((UseAVX == 3) && (MaxVectorSize >= 16));
|
predicate(UseAVX == 3);
|
||||||
|
|
||||||
effect(DEF dst, KILL cr,
|
effect(DEF dst, KILL cr,
|
||||||
KILL x0, KILL x1, KILL x2, KILL x3,
|
KILL x0, KILL x1, KILL x2, KILL x3,
|
||||||
|
40
src/hotspot/os_cpu/linux_x86/gc/z/zArguments_linux_x86.cpp
Normal file
40
src/hotspot/os_cpu/linux_x86/gc/z/zArguments_linux_x86.cpp
Normal file
@ -0,0 +1,40 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved.
|
||||||
|
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||||
|
*
|
||||||
|
* This code is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License version 2 only, as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This code is distributed in the hope that it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||||
|
* version 2 for more details (a copy is included in the LICENSE file that
|
||||||
|
* accompanied this code).
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License version
|
||||||
|
* 2 along with this work; if not, write to the Free Software Foundation,
|
||||||
|
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
*
|
||||||
|
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
|
||||||
|
* or visit www.oracle.com if you need additional information or have any
|
||||||
|
* questions.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "precompiled.hpp"
|
||||||
|
#include "gc/z/zArguments.hpp"
|
||||||
|
#include "runtime/globals.hpp"
|
||||||
|
#include "runtime/globals_extension.hpp"
|
||||||
|
#include "utilities/debug.hpp"
|
||||||
|
|
||||||
|
void ZArguments::initialize_platform() {
|
||||||
|
// The C2 barrier slow path expects vector registers to be least
|
||||||
|
// 16 bytes wide, which is the minimum width available on all
|
||||||
|
// x86-64 systems. However, the user could have speficied a lower
|
||||||
|
// number on the command-line, in which case we print a warning
|
||||||
|
// and raise it to 16.
|
||||||
|
if (MaxVectorSize < 16) {
|
||||||
|
warning("ZGC requires MaxVectorSize to be at least 16");
|
||||||
|
FLAG_SET_DEFAULT(MaxVectorSize, 16);
|
||||||
|
}
|
||||||
|
}
|
@ -19,7 +19,6 @@
|
|||||||
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
|
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
|
||||||
* or visit www.oracle.com if you need additional information or have any
|
* or visit www.oracle.com if you need additional information or have any
|
||||||
* questions.
|
* questions.
|
||||||
*
|
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "precompiled.hpp"
|
#include "precompiled.hpp"
|
||||||
@ -91,6 +90,9 @@ void ZArguments::initialize() {
|
|||||||
// Verification of stacks not (yet) supported, for the same reason
|
// Verification of stacks not (yet) supported, for the same reason
|
||||||
// we need fixup_partial_loads
|
// we need fixup_partial_loads
|
||||||
DEBUG_ONLY(FLAG_SET_DEFAULT(VerifyStack, false));
|
DEBUG_ONLY(FLAG_SET_DEFAULT(VerifyStack, false));
|
||||||
|
|
||||||
|
// Initialize platform specific arguments
|
||||||
|
initialize_platform();
|
||||||
}
|
}
|
||||||
|
|
||||||
CollectedHeap* ZArguments::create_heap() {
|
CollectedHeap* ZArguments::create_heap() {
|
||||||
|
@ -29,6 +29,9 @@
|
|||||||
class CollectedHeap;
|
class CollectedHeap;
|
||||||
|
|
||||||
class ZArguments : public GCArguments {
|
class ZArguments : public GCArguments {
|
||||||
|
private:
|
||||||
|
void initialize_platform();
|
||||||
|
|
||||||
public:
|
public:
|
||||||
virtual void initialize();
|
virtual void initialize();
|
||||||
virtual size_t conservative_max_heap_alignment();
|
virtual size_t conservative_max_heap_alignment();
|
||||||
|
Loading…
x
Reference in New Issue
Block a user