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8138952: C1: Distinguish between PPC32 and PPC64

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Reviewed-by: twisti, goetz, vlivanov
This commit is contained in:
Martin Doerr 2015-11-23 11:06:14 +01:00
parent a51ff63df7
commit 2952cd0bde
12 changed files with 48 additions and 36 deletions
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7
hotspot/src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.hpp
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@ -1,6 +1,6 @@
/* /*
* Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved. * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* *
* This code is free software; you can redistribute it and/or modify it * This code is free software; you can redistribute it and/or modify it
@ -105,4 +105,7 @@ void zero_memory(Register addr, Register len, Register t1);
void invalidate_registers(bool inv_r0, bool inv_r19, bool inv_r2, bool inv_r3, bool inv_r4, bool inv_r5) PRODUCT_RETURN; void invalidate_registers(bool inv_r0, bool inv_r19, bool inv_r2, bool inv_r3, bool inv_r4, bool inv_r5) PRODUCT_RETURN;
// This platform only uses signal-based null checks. The Label is not needed.
void null_check(Register r, Label *Lnull = NULL) { MacroAssembler::null_check(r); }
#endif // CPU_AARCH64_VM_C1_MACROASSEMBLER_AARCH64_HPP #endif // CPU_AARCH64_VM_C1_MACROASSEMBLER_AARCH64_HPP

5
hotspot/src/cpu/sparc/vm/c1_MacroAssembler_sparc.hpp
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 1999, 2011, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* *
* This code is free software; you can redistribute it and/or modify it * This code is free software; you can redistribute it and/or modify it
@ -88,4 +88,7 @@
void invalidate_registers(bool iregisters, bool lregisters, bool oregisters, void invalidate_registers(bool iregisters, bool lregisters, bool oregisters,
Register preserve1 = noreg, Register preserve2 = noreg); Register preserve1 = noreg, Register preserve2 = noreg);
// This platform only uses signal-based null checks. The Label is not needed.
void null_check(Register r, Label *Lnull = NULL) { MacroAssembler::null_check(r); }
#endif // CPU_SPARC_VM_C1_MACROASSEMBLER_SPARC_HPP #endif // CPU_SPARC_VM_C1_MACROASSEMBLER_SPARC_HPP

5
hotspot/src/cpu/x86/vm/c1_MacroAssembler_x86.hpp
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* *
* This code is free software; you can redistribute it and/or modify it * This code is free software; you can redistribute it and/or modify it
@ -117,4 +117,7 @@
void invalidate_registers(bool inv_rax, bool inv_rbx, bool inv_rcx, bool inv_rdx, bool inv_rsi, bool inv_rdi) PRODUCT_RETURN; void invalidate_registers(bool inv_rax, bool inv_rbx, bool inv_rcx, bool inv_rdx, bool inv_rsi, bool inv_rdi) PRODUCT_RETURN;
// This platform only uses signal-based null checks. The Label is not needed.
void null_check(Register r, Label *Lnull = NULL) { MacroAssembler::null_check(r); }
#endif // CPU_X86_VM_C1_MACROASSEMBLER_X86_HPP #endif // CPU_X86_VM_C1_MACROASSEMBLER_X86_HPP

4
hotspot/src/share/vm/c1/c1_Compilation.hpp
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* *
* This code is free software; you can redistribute it and/or modify it * This code is free software; you can redistribute it and/or modify it
@ -192,7 +192,7 @@ class Compilation: public StackObj {
const char* bailout_msg() const { return _bailout_msg; } const char* bailout_msg() const { return _bailout_msg; }
static int desired_max_code_buffer_size() { static int desired_max_code_buffer_size() {
#ifndef PPC #ifndef PPC32
return (int) NMethodSizeLimit; // default 256K or 512K return (int) NMethodSizeLimit; // default 256K or 512K
#else #else
// conditional branches on PPC are restricted to 16 bit signed // conditional branches on PPC are restricted to 16 bit signed

16
hotspot/src/share/vm/c1/c1_LIR.cpp
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@ -55,7 +55,7 @@ XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
#endif // X86 #endif // X86
#if defined(SPARC) || defined(PPC) #if defined(SPARC) || defined(PPC32)
FloatRegister LIR_OprDesc::as_float_reg() const { FloatRegister LIR_OprDesc::as_float_reg() const {
return FrameMap::nr2floatreg(fpu_regnr()); return FrameMap::nr2floatreg(fpu_regnr());
@ -67,7 +67,7 @@ FloatRegister LIR_OprDesc::as_double_reg() const {
#endif #endif
#if defined(ARM) || defined (AARCH64) #if defined(ARM) || defined(AARCH64) || defined(PPC64)
FloatRegister LIR_OprDesc::as_float_reg() const { FloatRegister LIR_OprDesc::as_float_reg() const {
return as_FloatRegister(fpu_regnr()); return as_FloatRegister(fpu_regnr());
@ -207,17 +207,17 @@ void LIR_OprDesc::validate_type() const {
size_field() == double_size, "must match"); size_field() == double_size, "must match");
break; break;
case T_FLOAT: case T_FLOAT:
// FP return values can be also in CPU registers on ARM and PPC (softfp ABI) // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI)
assert((kindfield == fpu_register || kindfield == stack_value assert((kindfield == fpu_register || kindfield == stack_value
ARM_ONLY(|| kindfield == cpu_register) ARM_ONLY(|| kindfield == cpu_register)
PPC_ONLY(|| kindfield == cpu_register) ) && PPC32_ONLY(|| kindfield == cpu_register) ) &&
size_field() == single_size, "must match"); size_field() == single_size, "must match");
break; break;
case T_DOUBLE: case T_DOUBLE:
// FP return values can be also in CPU registers on ARM and PPC (softfp ABI) // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI)
assert((kindfield == fpu_register || kindfield == stack_value assert((kindfield == fpu_register || kindfield == stack_value
ARM_ONLY(|| kindfield == cpu_register) ARM_ONLY(|| kindfield == cpu_register)
PPC_ONLY(|| kindfield == cpu_register) ) && PPC32_ONLY(|| kindfield == cpu_register) ) &&
size_field() == double_size, "must match"); size_field() == double_size, "must match");
break; break;
case T_BOOLEAN: case T_BOOLEAN:
@ -558,7 +558,7 @@ void LIR_OpVisitState::visit(LIR_Op* op) {
assert(opConvert->_info == NULL, "must be"); assert(opConvert->_info == NULL, "must be");
if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
if (opConvert->_result->is_valid()) do_output(opConvert->_result); if (opConvert->_result->is_valid()) do_output(opConvert->_result);
#ifdef PPC #ifdef PPC32
if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
#endif #endif
@ -1953,7 +1953,7 @@ void LIR_OpConvert::print_instr(outputStream* out) const {
print_bytecode(out, bytecode()); print_bytecode(out, bytecode());
in_opr()->print(out); out->print(" "); in_opr()->print(out); out->print(" ");
result_opr()->print(out); out->print(" "); result_opr()->print(out); out->print(" ");
#ifdef PPC #ifdef PPC32
if(tmp1()->is_valid()) { if(tmp1()->is_valid()) {
tmp1()->print(out); out->print(" "); tmp1()->print(out); out->print(" ");
tmp2()->print(out); out->print(" "); tmp2()->print(out); out->print(" ");

16
hotspot/src/share/vm/c1/c1_LIR.hpp
View File

@ -648,12 +648,14 @@ class LIR_OprFact: public AllStatic {
LIR_OprDesc::double_size | LIR_OprDesc::double_size |
LIR_OprDesc::is_xmm_mask); } LIR_OprDesc::is_xmm_mask); }
#endif // X86 #endif // X86
#ifdef PPC #if defined(PPC)
static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
(reg << LIR_OprDesc::reg2_shift) | (reg << LIR_OprDesc::reg2_shift) |
LIR_OprDesc::double_type | LIR_OprDesc::double_type |
LIR_OprDesc::fpu_register | LIR_OprDesc::fpu_register |
LIR_OprDesc::double_size); } LIR_OprDesc::double_size); }
#endif
#ifdef PPC32
static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) | static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) |
LIR_OprDesc::float_type | LIR_OprDesc::float_type |
LIR_OprDesc::cpu_register | LIR_OprDesc::cpu_register |
@ -663,7 +665,7 @@ class LIR_OprFact: public AllStatic {
LIR_OprDesc::double_type | LIR_OprDesc::double_type |
LIR_OprDesc::cpu_register | LIR_OprDesc::cpu_register |
LIR_OprDesc::double_size); } LIR_OprDesc::double_size); }
#endif // PPC #endif // PPC32
static LIR_Opr virtual_register(int index, BasicType type) { static LIR_Opr virtual_register(int index, BasicType type) {
LIR_Opr res; LIR_Opr res;
@ -1475,7 +1477,7 @@ class LIR_OpConvert: public LIR_Op1 {
private: private:
Bytecodes::Code _bytecode; Bytecodes::Code _bytecode;
ConversionStub* _stub; ConversionStub* _stub;
#ifdef PPC #ifdef PPC32
LIR_Opr _tmp1; LIR_Opr _tmp1;
LIR_Opr _tmp2; LIR_Opr _tmp2;
#endif #endif
@ -1484,13 +1486,13 @@ class LIR_OpConvert: public LIR_Op1 {
LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub) LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub)
: LIR_Op1(lir_convert, opr, result) : LIR_Op1(lir_convert, opr, result)
, _stub(stub) , _stub(stub)
#ifdef PPC #ifdef PPC32
, _tmp1(LIR_OprDesc::illegalOpr()) , _tmp1(LIR_OprDesc::illegalOpr())
, _tmp2(LIR_OprDesc::illegalOpr()) , _tmp2(LIR_OprDesc::illegalOpr())
#endif #endif
, _bytecode(code) {} , _bytecode(code) {}
#ifdef PPC #ifdef PPC32
LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub
,LIR_Opr tmp1, LIR_Opr tmp2) ,LIR_Opr tmp1, LIR_Opr tmp2)
: LIR_Op1(lir_convert, opr, result) : LIR_Op1(lir_convert, opr, result)
@ -1502,7 +1504,7 @@ class LIR_OpConvert: public LIR_Op1 {
Bytecodes::Code bytecode() const { return _bytecode; } Bytecodes::Code bytecode() const { return _bytecode; }
ConversionStub* stub() const { return _stub; } ConversionStub* stub() const { return _stub; }
#ifdef PPC #ifdef PPC32
LIR_Opr tmp1() const { return _tmp1; } LIR_Opr tmp1() const { return _tmp1; }
LIR_Opr tmp2() const { return _tmp2; } LIR_Opr tmp2() const { return _tmp2; }
#endif #endif
@ -2142,7 +2144,7 @@ class LIR_List: public CompilationResourceObj {
void safepoint(LIR_Opr tmp, CodeEmitInfo* info) { append(new LIR_Op1(lir_safepoint, tmp, info)); } void safepoint(LIR_Opr tmp, CodeEmitInfo* info) { append(new LIR_Op1(lir_safepoint, tmp, info)); }
#ifdef PPC #ifdef PPC32
void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, LIR_Opr tmp1, LIR_Opr tmp2) { append(new LIR_OpConvert(code, left, dst, NULL, tmp1, tmp2)); } void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, LIR_Opr tmp1, LIR_Opr tmp2) { append(new LIR_OpConvert(code, left, dst, NULL, tmp1, tmp2)); }
#endif #endif
void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL/*, bool is_32bit = false*/) { append(new LIR_OpConvert(code, left, dst, stub)); } void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL/*, bool is_32bit = false*/) { append(new LIR_OpConvert(code, left, dst, stub)); }

13
hotspot/src/share/vm/c1/c1_LIRAssembler.cpp
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* *
* This code is free software; you can redistribute it and/or modify it * This code is free software; you can redistribute it and/or modify it
@ -413,13 +413,14 @@ void LIR_Assembler::record_non_safepoint_debug_info() {
} }
void LIR_Assembler::add_debug_info_for_null_check_here(CodeEmitInfo* cinfo) { ImplicitNullCheckStub* LIR_Assembler::add_debug_info_for_null_check_here(CodeEmitInfo* cinfo) {
add_debug_info_for_null_check(code_offset(), cinfo); return add_debug_info_for_null_check(code_offset(), cinfo);
} }
void LIR_Assembler::add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo) { ImplicitNullCheckStub* LIR_Assembler::add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo) {
ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(pc_offset, cinfo); ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(pc_offset, cinfo);
append_code_stub(stub); append_code_stub(stub);
return stub;
} }
void LIR_Assembler::add_debug_info_for_div0_here(CodeEmitInfo* info) { void LIR_Assembler::add_debug_info_for_div0_here(CodeEmitInfo* info) {
@ -557,10 +558,10 @@ void LIR_Assembler::emit_op1(LIR_Op1* op) {
case lir_null_check: case lir_null_check:
if (GenerateCompilerNullChecks) { if (GenerateCompilerNullChecks) {
add_debug_info_for_null_check_here(op->info()); ImplicitNullCheckStub* stub = add_debug_info_for_null_check_here(op->info());
if (op->in_opr()->is_single_cpu()) { if (op->in_opr()->is_single_cpu()) {
_masm->null_check(op->in_opr()->as_register()); _masm->null_check(op->in_opr()->as_register(), stub->entry());
} else { } else {
Unimplemented(); Unimplemented();
} }

4
hotspot/src/share/vm/c1/c1_LIRAssembler.hpp
View File

@ -99,8 +99,8 @@ class LIR_Assembler: public CompilationResourceObj {
void add_debug_info_for_branch(CodeEmitInfo* info); void add_debug_info_for_branch(CodeEmitInfo* info);
void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo); void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo);
void add_debug_info_for_div0_here(CodeEmitInfo* info); void add_debug_info_for_div0_here(CodeEmitInfo* info);
void add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo); ImplicitNullCheckStub* add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo);
void add_debug_info_for_null_check_here(CodeEmitInfo* info); ImplicitNullCheckStub* add_debug_info_for_null_check_here(CodeEmitInfo* info);
void set_24bit_FPU(); void set_24bit_FPU();
void reset_FPU(); void reset_FPU();

4
hotspot/src/share/vm/c1/c1_LinearScan.cpp
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@ -2087,7 +2087,7 @@ LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
#ifdef _LP64 #ifdef _LP64
return LIR_OprFact::double_cpu(assigned_reg, assigned_reg); return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
#else #else
#if defined(SPARC) || defined(PPC) #if defined(SPARC) || defined(PPC32)
return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg); return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
#else #else
return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi); return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
@ -2728,7 +2728,7 @@ int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeV
#ifdef ARM32 #ifdef ARM32
assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)"); assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
#endif #endif
#ifdef PPC #ifdef PPC32
assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)"); assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
#endif #endif

6
hotspot/src/share/vm/c1/c1_Runtime1.cpp
View File

@ -210,7 +210,7 @@ void Runtime1::generate_blob_for(BufferBlob* buffer_blob, StubID id) {
case fpu2long_stub_id: case fpu2long_stub_id:
case unwind_exception_id: case unwind_exception_id:
case counter_overflow_id: case counter_overflow_id:
#if defined(SPARC) || defined(PPC) #if defined(SPARC) || defined(PPC32)
case handle_exception_nofpu_id: // Unused on sparc case handle_exception_nofpu_id: // Unused on sparc
#endif #endif
break; break;
@ -1097,7 +1097,7 @@ JRT_ENTRY(void, Runtime1::patch_code(JavaThread* thread, Runtime1::StubID stub_i
ShouldNotReachHere(); ShouldNotReachHere();
} }
#if defined(SPARC) || defined(PPC) #if defined(SPARC) || defined(PPC32)
if (load_klass_or_mirror_patch_id || if (load_klass_or_mirror_patch_id ||
stub_id == Runtime1::load_appendix_patching_id) { stub_id == Runtime1::load_appendix_patching_id) {
// Update the location in the nmethod with the proper // Update the location in the nmethod with the proper
@ -1195,7 +1195,7 @@ JRT_ENTRY(void, Runtime1::patch_code(JavaThread* thread, Runtime1::StubID stub_i
relocInfo::change_reloc_info_for_address(&iter2, (address) instr_pc2, relocInfo::change_reloc_info_for_address(&iter2, (address) instr_pc2,
relocInfo::none, rtype); relocInfo::none, rtype);
#endif #endif
#ifdef PPC #ifdef PPC32
{ address instr_pc2 = instr_pc + NativeMovConstReg::lo_offset; { address instr_pc2 = instr_pc + NativeMovConstReg::lo_offset;
RelocIterator iter2(nm, instr_pc2, instr_pc2 + 1); RelocIterator iter2(nm, instr_pc2, instr_pc2 + 1);
relocInfo::change_reloc_info_for_address(&iter2, (address) instr_pc2, relocInfo::change_reloc_info_for_address(&iter2, (address) instr_pc2,

2
hotspot/src/share/vm/runtime/sharedRuntime.cpp
View File

@ -386,7 +386,7 @@ double SharedRuntime::dabs(double f) {
#endif #endif
#if defined(__SOFTFP__) || defined(PPC32) #if defined(__SOFTFP__) || defined(PPC)
double SharedRuntime::dsqrt(double f) { double SharedRuntime::dsqrt(double f) {
return sqrt(f); return sqrt(f);
} }

2
hotspot/src/share/vm/runtime/sharedRuntime.hpp
View File

@ -141,7 +141,7 @@ class SharedRuntime: AllStatic {
static double dabs(double f); static double dabs(double f);
#endif #endif
#if defined(__SOFTFP__) || defined(PPC32) #if defined(__SOFTFP__) || defined(PPC)
static double dsqrt(double f); static double dsqrt(double f);
#endif #endif