8308656: RISC-V: vstring_compare doesnt manifest usage of all vector registers

Reviewed-by: yzhu, fyang
This commit is contained in:
Vladimir Kempik 2023-05-25 05:08:39 +00:00
parent a291f002cd
commit 2a18e537d6
2 changed files with 36 additions and 4 deletions
src/hotspot/cpu/riscv

@ -904,6 +904,16 @@ reg_class v5_reg(
V5, V5_H, V5_J, V5_K
);
// class for vector register v6
reg_class v6_reg(
V6, V6_H, V6_J, V6_K
);
// class for vector register v7
reg_class v7_reg(
V7, V7_H, V7_J, V7_K
);
// class for condition codes
reg_class reg_flags(RFLAGS);
@ -3598,6 +3608,26 @@ operand vReg_V5()
interface(REG_INTER);
%}
operand vReg_V6()
%{
constraint(ALLOC_IN_RC(v6_reg));
match(VecA);
match(vReg);
op_cost(0);
format %{ %}
interface(REG_INTER);
%}
operand vReg_V7()
%{
constraint(ALLOC_IN_RC(v7_reg));
match(VecA);
match(vReg);
op_cost(0);
format %{ %}
interface(REG_INTER);
%}
operand vRegMask()
%{
constraint(ALLOC_IN_RC(vmask_reg));

@ -3129,13 +3129,14 @@ instruct vstring_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_
%}
instruct vstring_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
iRegI_R10 result, vReg_V1 v1, vReg_V2 v2, vReg_V3 v3, vReg_V4 v4, vReg_V5 v5,
iRegI_R10 result, vReg_V1 v1, vReg_V2 v2, vReg_V3 v3, vReg_V4 v4,
vReg_V5 v5, vReg_V6 v6, vReg_V7 v7,
vRegMask_V0 v0, iRegP_R28 tmp1, iRegL_R29 tmp2)
%{
predicate(UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
match(Set result(StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
effect(KILL tmp1, KILL tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2,
TEMP v1, TEMP v2, TEMP v3, TEMP v4, TEMP v5, TEMP v0);
TEMP v1, TEMP v2, TEMP v3, TEMP v4, TEMP v5, TEMP v6, TEMP v7, TEMP v0);
format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
ins_encode %{
@ -3147,13 +3148,14 @@ instruct vstring_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI
ins_pipe(pipe_class_memory);
%}
instruct vstring_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
iRegI_R10 result, vReg_V1 v1, vReg_V2 v2, vReg_V3 v3, vReg_V4 v4, vReg_V5 v5,
iRegI_R10 result, vReg_V1 v1, vReg_V2 v2, vReg_V3 v3, vReg_V4 v4,
vReg_V5 v5, vReg_V6 v6, vReg_V7 v7,
vRegMask_V0 v0, iRegP_R28 tmp1, iRegL_R29 tmp2)
%{
predicate(UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
match(Set result(StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
effect(KILL tmp1, KILL tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2,
TEMP v1, TEMP v2, TEMP v3, TEMP v4, TEMP v5, TEMP v0);
TEMP v1, TEMP v2, TEMP v3, TEMP v4, TEMP v5, TEMP v6, TEMP v7, TEMP v0);
format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
ins_encode %{