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8284990: AArch64: Remove STXR_PREFETCH from CPU features

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Reviewed-by: aph, ngasson, njian
This commit is contained in:
Eric Liu 2022-07-27 09:38:04 +00:00 committed by Nick Gasson
parent 2a1d9cfead
commit 2bd90c2149
5 changed files with 7 additions and 18 deletions
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6
src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
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@ -1892,7 +1892,6 @@ void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register t
return; return;
} }
Label retry_load; Label retry_load;
if (VM_Version::supports_stxr_prefetch())
prfm(Address(counter_addr), PSTL1STRM); prfm(Address(counter_addr), PSTL1STRM);
bind(retry_load); bind(retry_load);
// flush and load exclusive from the memory location // flush and load exclusive from the memory location
@ -2627,7 +2626,6 @@ void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Reg
membar(AnyAny); membar(AnyAny);
} else { } else {
Label retry_load, nope; Label retry_load, nope;
if (VM_Version::supports_stxr_prefetch())
prfm(Address(addr), PSTL1STRM); prfm(Address(addr), PSTL1STRM);
bind(retry_load); bind(retry_load);
// flush and load exclusive from the memory location // flush and load exclusive from the memory location
@ -2670,7 +2668,6 @@ void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Regis
membar(AnyAny); membar(AnyAny);
} else { } else {
Label retry_load, nope; Label retry_load, nope;
if (VM_Version::supports_stxr_prefetch())
prfm(Address(addr), PSTL1STRM); prfm(Address(addr), PSTL1STRM);
bind(retry_load); bind(retry_load);
// flush and load exclusive from the memory location // flush and load exclusive from the memory location
@ -2712,7 +2709,6 @@ void MacroAssembler::cmpxchg(Register addr, Register expected,
compare_eq(result, expected, size); compare_eq(result, expected, size);
} else { } else {
Label retry_load, done; Label retry_load, done;
if (VM_Version::supports_stxr_prefetch())
prfm(Address(addr), PSTL1STRM); prfm(Address(addr), PSTL1STRM);
bind(retry_load); bind(retry_load);
load_exclusive(result, addr, size, acquire); load_exclusive(result, addr, size, acquire);
@ -2771,7 +2767,6 @@ void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Regis
result = different(prev, incr, addr) ? prev : rscratch2; \ result = different(prev, incr, addr) ? prev : rscratch2; \
\ \
Label retry_load; \ Label retry_load; \
if (VM_Version::supports_stxr_prefetch()) \
prfm(Address(addr), PSTL1STRM); \ prfm(Address(addr), PSTL1STRM); \
bind(retry_load); \ bind(retry_load); \
LDXR(result, addr); \ LDXR(result, addr); \
@ -2802,7 +2797,6 @@ void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) {
result = different(prev, newv, addr) ? prev : rscratch2; \ result = different(prev, newv, addr) ? prev : rscratch2; \
\ \
Label retry_load; \ Label retry_load; \
if (VM_Version::supports_stxr_prefetch()) \
prfm(Address(addr), PSTL1STRM); \ prfm(Address(addr), PSTL1STRM); \
bind(retry_load); \ bind(retry_load); \
LDXR(result, addr); \ LDXR(result, addr); \

2
src/hotspot/cpu/aarch64/vm_version_aarch64.cpp
View File

@ -223,8 +223,6 @@ void VM_Version::initialize() {
} }
} }
if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH;
char buf[512]; char buf[512];
sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision); sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2); if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);

1
src/hotspot/cpu/aarch64/vm_version_aarch64.hpp
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@ -120,7 +120,6 @@ public:
/* flags above must follow Linux HWCAP */ \ /* flags above must follow Linux HWCAP */ \
decl(SVEBITPERM, svebitperm, 27) \ decl(SVEBITPERM, svebitperm, 27) \
decl(SVE2, sve2, 28) \ decl(SVE2, sve2, 28) \
decl(STXR_PREFETCH, stxr_prefetch, 29) \
decl(A53MAC, a53mac, 31) decl(A53MAC, a53mac, 31)
enum Feature_Flag { enum Feature_Flag {

1
src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.aarch64/src/jdk/vm/ci/aarch64/AArch64.java
View File

@ -180,7 +180,6 @@ public class AArch64 extends Architecture {
PACA, PACA,
SVEBITPERM, SVEBITPERM,
SVE2, SVE2,
STXR_PREFETCH,
A53MAC, A53MAC,
} }

3
src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.aarch64/src/jdk/vm/ci/hotspot/aarch64/AArch64HotSpotVMConfig.java
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016, 2020, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* *
* This code is free software; you can redistribute it and/or modify it * This code is free software; you can redistribute it and/or modify it
@ -68,7 +68,6 @@ class AArch64HotSpotVMConfig extends HotSpotVMConfigAccess {
final long aarch64SHA2 = getConstant("VM_Version::CPU_SHA2", Long.class); final long aarch64SHA2 = getConstant("VM_Version::CPU_SHA2", Long.class);
final long aarch64CRC32 = getConstant("VM_Version::CPU_CRC32", Long.class); final long aarch64CRC32 = getConstant("VM_Version::CPU_CRC32", Long.class);
final long aarch64LSE = getConstant("VM_Version::CPU_LSE", Long.class); final long aarch64LSE = getConstant("VM_Version::CPU_LSE", Long.class);
final long aarch64STXR_PREFETCH = getConstant("VM_Version::CPU_STXR_PREFETCH", Long.class);
final long aarch64A53MAC = getConstant("VM_Version::CPU_A53MAC", Long.class); final long aarch64A53MAC = getConstant("VM_Version::CPU_A53MAC", Long.class);
// Checkstyle: resume // Checkstyle: resume
} }