8321001: RISC-V: C2 SignumVF
8321002: RISC-V: C2 SignumVD Reviewed-by: fyang
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parent
de95259306
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src/hotspot/cpu/riscv
test/hotspot/jtreg/compiler/vectorization
@ -1417,6 +1417,7 @@ enum VectorMask {
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INSN(vmfeq_vv, 0b1010111, 0b001, 0b011000);
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// Vector Floating-Point Sign-Injection Instructions
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INSN(vfsgnj_vv, 0b1010111, 0b001, 0b001000);
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INSN(vfsgnjx_vv, 0b1010111, 0b001, 0b001010);
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INSN(vfsgnjn_vv, 0b1010111, 0b001, 0b001001);
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@ -1677,6 +1677,19 @@ void C2_MacroAssembler::signum_fp(FloatRegister dst, FloatRegister one, bool is_
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bind(done);
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}
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void C2_MacroAssembler::signum_fp_v(VectorRegister dst, VectorRegister one, BasicType bt, int vlen) {
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vsetvli_helper(bt, vlen);
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// check if input is -0, +0, signaling NaN or quiet NaN
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vfclass_v(v0, dst);
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mv(t0, fclass_mask::zero | fclass_mask::nan);
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vand_vx(v0, v0, t0);
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vmseq_vi(v0, v0, 0);
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// use floating-point 1.0 with a sign of input
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vfsgnj_vv(dst, one, dst, v0_t);
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}
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void C2_MacroAssembler::compress_bits_v(Register dst, Register src, Register mask, bool is_long) {
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Assembler::SEW sew = is_long ? Assembler::e64 : Assembler::e32;
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// intrinsic is enabled when MaxVectorSize >= 16
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@ -163,6 +163,8 @@
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void signum_fp(FloatRegister dst, FloatRegister one, bool is_double);
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void signum_fp_v(VectorRegister dst, VectorRegister one, BasicType bt, int vlen);
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// intrinsic methods implemented by rvv instructions
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// compress bits, i.e. j.l.Integer/Long::compress.
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@ -3660,6 +3660,23 @@ instruct vexpand(vReg dst, vReg src, vRegMask_V0 v0, vReg tmp) %{
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ins_pipe(pipe_slow);
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%}
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// ------------------------------ Vector signum --------------------------------
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// Vector Math.signum
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instruct vsignum_reg(vReg dst, vReg zero, vReg one, vRegMask_V0 v0) %{
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match(Set dst (SignumVF dst (Binary zero one)));
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match(Set dst (SignumVD dst (Binary zero one)));
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effect(TEMP_DEF dst, TEMP v0);
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format %{ "vsignum $dst, $dst\t" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ signum_fp_v(as_VectorRegister($dst$$reg), as_VectorRegister($one$$reg),
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bt, Matcher::vector_length(this));
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%}
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ins_pipe(pipe_slow);
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%}
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// ------------------------------ Vector Load Gather ---------------------------
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instruct gather_load(vReg dst, indirect mem, vReg idx) %{
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@ -24,9 +24,11 @@
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/**
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* @test
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* @bug 8282711 8290249
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* @summary Accelerate Math.signum function for AVX, AVX512 and aarch64 (Neon and SVE)
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* @summary Accelerate Math.signum function for AVX, AVX512, aarch64 (Neon and SVE)
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* and riscv64 (vector)
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* @requires vm.compiler2.enabled
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* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx.*") | os.arch == "aarch64"
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* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx.*") | os.arch == "aarch64" |
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* (os.arch == "riscv64" & vm.cpu.features ~= ".*v,.*")
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* @library /test/lib /
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* @run driver compiler.vectorization.TestSignumVector
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*/
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