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8302776: RISC-V: Fix typo CSR_INSTERT to CSR_INSTRET

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Reviewed-by: fyang
This commit is contained in:
Ludovic Henry 2023-02-20 10:48:27 +00:00
parent 7c40c8af69
commit 303c61f3ca
2 changed files with 2 additions and 2 deletions
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2
src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
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@ -1059,7 +1059,7 @@ void MacroAssembler::wrap_label(Register r1, Register r2, Label &L,
csrr(Rd, CSR); \ csrr(Rd, CSR); \
} }
INSN(rdinstret, CSR_INSTERT); INSN(rdinstret, CSR_INSTRET);
INSN(rdcycle, CSR_CYCLE); INSN(rdcycle, CSR_CYCLE);
INSN(rdtime, CSR_TIME); INSN(rdtime, CSR_TIME);
INSN(frcsr, CSR_FCSR); INSN(frcsr, CSR_FCSR);

2
src/hotspot/cpu/riscv/register_riscv.hpp
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@ -41,7 +41,7 @@
#define CSR_VLENB 0xC22 // VLEN/8 (vector register length in bytes) #define CSR_VLENB 0xC22 // VLEN/8 (vector register length in bytes)
#define CSR_CYCLE 0xc00 // Cycle counter for RDCYCLE instruction. #define CSR_CYCLE 0xc00 // Cycle counter for RDCYCLE instruction.
#define CSR_TIME 0xc01 // Timer for RDTIME instruction. #define CSR_TIME 0xc01 // Timer for RDTIME instruction.
#define CSR_INSTERT 0xc02 // Instructions-retired counter for RDINSTRET instruction. #define CSR_INSTRET 0xc02 // Instructions-retired counter for RDINSTRET instruction.
class VMRegImpl; class VMRegImpl;
typedef VMRegImpl* VMReg; typedef VMRegImpl* VMReg;