8320069: RISC-V: Add Zcb instructions
Reviewed-by: fyang, vkempik
This commit is contained in:
parent
4cf131a101
commit
30f93a29c2
src/hotspot
@ -506,7 +506,7 @@ public:
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INSN(sllw, 0b0111011, 0b001, 0b0000000);
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INSN(sraw, 0b0111011, 0b101, 0b0100000);
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INSN(srlw, 0b0111011, 0b101, 0b0000000);
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INSN(mul, 0b0110011, 0b000, 0b0000001);
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INSN(_mul, 0b0110011, 0b000, 0b0000001);
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INSN(mulh, 0b0110011, 0b001, 0b0000001);
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INSN(mulhsu,0b0110011, 0b010, 0b0000001);
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INSN(mulhu, 0b0110011, 0b011, 0b0000001);
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@ -537,9 +537,9 @@ public:
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}
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INSN(lb, 0b0000011, 0b000);
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INSN(lbu, 0b0000011, 0b100);
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INSN(lh, 0b0000011, 0b001);
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INSN(lhu, 0b0000011, 0b101);
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INSN(_lbu, 0b0000011, 0b100);
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INSN(_lh, 0b0000011, 0b001);
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INSN(_lhu, 0b0000011, 0b101);
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INSN(_lw, 0b0000011, 0b010);
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INSN(lwu, 0b0000011, 0b110);
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INSN(_ld, 0b0000011, 0b011);
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@ -609,8 +609,8 @@ public:
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emit(insn); \
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} \
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INSN(sb, Register, 0b0100011, 0b000);
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INSN(sh, Register, 0b0100011, 0b001);
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INSN(_sb, Register, 0b0100011, 0b000);
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INSN(_sh, Register, 0b0100011, 0b001);
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INSN(_sw, Register, 0b0100011, 0b010);
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INSN(_sd, Register, 0b0100011, 0b011);
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INSN(fsw, FloatRegister, 0b0100111, 0b010);
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@ -1938,9 +1938,9 @@ enum Nf {
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}
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INSN(rev8, 0b0010011, 0b101, 0b011010111000);
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INSN(sext_b, 0b0010011, 0b001, 0b011000000100);
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INSN(sext_h, 0b0010011, 0b001, 0b011000000101);
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INSN(zext_h, 0b0111011, 0b100, 0b000010000000);
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INSN(_sext_b, 0b0010011, 0b001, 0b011000000100);
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INSN(_sext_h, 0b0010011, 0b001, 0b011000000101);
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INSN(_zext_h, 0b0111011, 0b100, 0b000010000000);
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INSN(clz, 0b0010011, 0b001, 0b011000000000);
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INSN(clzw, 0b0011011, 0b001, 0b011000000000);
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INSN(ctz, 0b0010011, 0b001, 0b011000000001);
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@ -2652,6 +2652,15 @@ public:
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return UseRVC && in_compressible_region();
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}
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bool do_compress_zcb(Register reg1 = noreg, Register reg2 = noreg) const {
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return do_compress() && VM_Version::ext_Zcb.enabled() &&
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(reg1 == noreg || reg1->is_compressed_valid()) && (reg2 == noreg || reg2->is_compressed_valid());
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}
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bool do_compress_zcb_zbb(Register reg1 = noreg, Register reg2 = noreg) const {
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return do_compress_zcb(reg1, reg2) && UseZbb;
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}
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// --------------------------
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// Load/store register
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// --------------------------
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@ -2986,6 +2995,238 @@ public:
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#undef INSN
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// -------------- ZCB Instruction Definitions --------------
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// Zcb additional C instructions
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private:
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// Format CLH, c.lh/c.lhu
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template <bool Unsigned>
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void c_lh_if(Register Rd_Rs2, Register Rs1, uint32_t uimm) {
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assert_cond(uimm == 0 || uimm == 2);
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assert_cond(do_compress_zcb(Rd_Rs2, Rs1));
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uint16_t insn = 0;
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c_patch((address)&insn, 1, 0, 0b00);
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c_patch_compressed_reg((address)&insn, 2, Rd_Rs2);
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c_patch((address)&insn, 5, 5, (uimm & nth_bit(1)) >> 1);
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c_patch((address)&insn, 6, 6, Unsigned ? 0 : 1);
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c_patch_compressed_reg((address)&insn, 7, Rs1);
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c_patch((address)&insn, 12, 10, 0b001);
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c_patch((address)&insn, 15, 13, 0b100);
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emit_int16(insn);
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}
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template <bool Unsigned>
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void lh_c_mux(Register Rd_Rs2, Register Rs1, const int32_t uimm) {
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if (do_compress_zcb(Rd_Rs2, Rs1) &&
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(uimm == 0 || uimm == 2)) {
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c_lh_if<Unsigned>(Rd_Rs2, Rs1, uimm);
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} else {
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if (Unsigned) {
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_lhu(Rd_Rs2, Rs1, uimm);
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} else {
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_lh(Rd_Rs2, Rs1, uimm);
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}
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}
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}
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// Format CU, c.[sz]ext.*, c.not
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template <uint8_t InstructionType>
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void c_u_if(Register Rs1) {
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assert_cond(do_compress_zcb(Rs1));
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uint16_t insn = 0;
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c_patch((address)&insn, 1, 0, 0b01);
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c_patch((address)&insn, 4, 2, InstructionType);
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c_patch((address)&insn, 6, 5, 0b11);
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c_patch_compressed_reg((address)&insn, 7, Rs1);
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c_patch((address)&insn, 12, 10, 0b111);
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c_patch((address)&insn, 15, 13, 0b100);
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emit_int16(insn);
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}
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public:
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// Prerequisites: Zcb
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void c_lh(Register Rd_Rs2, Register Rs1, const int32_t uimm) { c_lh_if<false>(Rd_Rs2, Rs1, uimm); }
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void lh(Register Rd_Rs2, Register Rs1, const int32_t uimm) { lh_c_mux<false>(Rd_Rs2, Rs1, uimm); }
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// Prerequisites: Zcb
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void c_lhu(Register Rd_Rs2, Register Rs1, const int32_t uimm) { c_lh_if<true>(Rd_Rs2, Rs1, uimm); }
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void lhu(Register Rd_Rs2, Register Rs1, const int32_t uimm) { lh_c_mux<true>(Rd_Rs2, Rs1, uimm); }
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// Prerequisites: Zcb
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// Format CLB, single instruction
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void c_lbu(Register Rd_Rs2, Register Rs1, uint32_t uimm) {
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assert_cond(uimm <= 3);
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assert_cond(do_compress_zcb(Rd_Rs2, Rs1));
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uint16_t insn = 0;
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c_patch((address)&insn, 1, 0, 0b00);
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c_patch_compressed_reg((address)&insn, 2, Rd_Rs2);
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c_patch((address)&insn, 5, 5, (uimm & nth_bit(1)) >> 1);
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c_patch((address)&insn, 6, 6, (uimm & nth_bit(0)) >> 0);
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c_patch_compressed_reg((address)&insn, 7, Rs1);
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c_patch((address)&insn, 12, 10, 0b000);
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c_patch((address)&insn, 15, 13, 0b100);
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emit_int16(insn);
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}
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void lbu(Register Rd_Rs2, Register Rs1, const int32_t uimm) {
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if (do_compress_zcb(Rd_Rs2, Rs1) &&
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uimm >= 0 && uimm <= 3) {
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c_lbu(Rd_Rs2, Rs1, uimm);
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} else {
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_lbu(Rd_Rs2, Rs1, uimm);
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}
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}
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// Prerequisites: Zcb
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// Format CSB, single instruction
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void c_sb(Register Rd_Rs2, Register Rs1, uint32_t uimm) {
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assert_cond(uimm <= 3);
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assert_cond(do_compress_zcb(Rd_Rs2, Rs1));
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uint16_t insn = 0;
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c_patch((address)&insn, 1, 0, 0b00);
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c_patch_compressed_reg((address)&insn, 2, Rd_Rs2);
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c_patch((address)&insn, 5, 5, (uimm & nth_bit(1)) >> 1);
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c_patch((address)&insn, 6, 6, (uimm & nth_bit(0)) >> 0);
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c_patch_compressed_reg((address)&insn, 7, Rs1);
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c_patch((address)&insn, 12, 10, 0b010);
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c_patch((address)&insn, 15, 13, 0b100);
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emit_int16(insn);
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}
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void sb(Register Rd_Rs2, Register Rs1, const int32_t uimm) {
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if (do_compress_zcb(Rd_Rs2, Rs1) &&
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uimm >= 0 && uimm <= 3) {
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c_sb(Rd_Rs2, Rs1, uimm);
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} else {
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_sb(Rd_Rs2, Rs1, uimm);
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}
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}
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// Prerequisites: Zcb
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// Format CSH, single instruction
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void c_sh(Register Rd_Rs2, Register Rs1, uint32_t uimm) {
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assert_cond(uimm == 0 || uimm == 2);
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assert_cond(do_compress_zcb(Rd_Rs2, Rs1));
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uint16_t insn = 0;
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c_patch((address)&insn, 1, 0, 0b00);
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c_patch_compressed_reg((address)&insn, 2, Rd_Rs2);
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c_patch((address)&insn, 5, 5, (uimm & nth_bit(1)) >> 1);
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c_patch((address)&insn, 6, 6, 0);
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c_patch_compressed_reg((address)&insn, 7, Rs1);
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c_patch((address)&insn, 12, 10, 0b011);
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c_patch((address)&insn, 15, 13, 0b100);
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emit_int16(insn);
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}
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void sh(Register Rd_Rs2, Register Rs1, const int32_t uimm) {
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if (do_compress_zcb(Rd_Rs2, Rs1) &&
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(uimm == 0 || uimm == 2)) {
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c_sh(Rd_Rs2, Rs1, uimm);
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} else {
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_sh(Rd_Rs2, Rs1, uimm);
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}
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}
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// Prerequisites: Zcb
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// Format CS
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void c_zext_b(Register Rs1) {
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assert_cond(do_compress_zcb(Rs1));
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c_u_if<0b000>(Rs1);
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}
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// Prerequisites: Zbb
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void sext_b(Register Rd_Rs2, Register Rs1) {
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assert_cond(UseZbb);
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if (do_compress_zcb_zbb(Rd_Rs2, Rs1) && (Rd_Rs2 == Rs1)) {
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c_sext_b(Rd_Rs2);
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} else {
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_sext_b(Rd_Rs2, Rs1);
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}
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}
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// Prerequisites: Zcb, Zbb
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// Format CS
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void c_sext_b(Register Rs1) {
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c_u_if<0b001>(Rs1);
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}
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// Prerequisites: Zbb
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void zext_h(Register Rd_Rs2, Register Rs1) {
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assert_cond(UseZbb);
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if (do_compress_zcb_zbb(Rd_Rs2, Rs1) && (Rd_Rs2 == Rs1)) {
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c_zext_h(Rd_Rs2);
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} else {
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_zext_h(Rd_Rs2, Rs1);
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}
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}
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// Prerequisites: Zcb, Zbb
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// Format CS
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void c_zext_h(Register Rs1) {
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c_u_if<0b010>(Rs1);
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}
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// Prerequisites: Zbb
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void sext_h(Register Rd_Rs2, Register Rs1) {
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assert_cond(UseZbb);
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if (do_compress_zcb_zbb(Rd_Rs2, Rs1) && (Rd_Rs2 == Rs1)) {
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c_sext_h(Rd_Rs2);
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} else {
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_sext_h(Rd_Rs2, Rs1);
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}
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}
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// Prerequisites: Zcb, Zbb
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// Format CS
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void c_sext_h(Register Rs1) {
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c_u_if<0b011>(Rs1);
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}
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// Prerequisites: Zcb, Zba
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// Format CS
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void c_zext_w(Register Rs1) {
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c_u_if<0b100>(Rs1);
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}
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// Prerequisites: Zcb
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// Format CS
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void c_not(Register Rs1) {
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c_u_if<0b101>(Rs1);
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}
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// Prerequisites: Zcb (M or Zmmul)
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// Format CA, c.mul
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void c_mul(Register Rd_Rs1, Register Rs2) {
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uint16_t insn = 0;
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c_patch((address)&insn, 1, 0, 0b01);
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c_patch_compressed_reg((address)&insn, 2, Rs2);
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c_patch((address)&insn, 6, 5, 0b10);
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c_patch_compressed_reg((address)&insn, 7, Rd_Rs1);
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c_patch((address)&insn, 12, 10, 0b111);
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c_patch((address)&insn, 15, 13, 0b100);
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emit_int16(insn);
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}
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void mul(Register Rd, Register Rs1, Register Rs2) {
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if (Rd != Rs1 && Rd != Rs2) {
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// Three registers needed without a mv, emit uncompressed
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_mul(Rd, Rs1, Rs2);
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return;
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}
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// Rd is either Rs1 or Rs2
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if (!do_compress_zcb(Rs2, Rs1)) {
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_mul(Rd, Rs1, Rs2);
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} else {
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if (Rd == Rs2) {
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Rs2 = Rs1;
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} else {
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assert(Rd == Rs1, "must be");
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}
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c_mul(Rd, Rs2);
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}
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}
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// Stack overflow checking
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virtual void bang_stack_with_offset(int offset) { Unimplemented(); }
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@ -4678,41 +4678,54 @@ void MacroAssembler::shadd(Register Rd, Register Rs1, Register Rs2, Register tmp
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}
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void MacroAssembler::zero_extend(Register dst, Register src, int bits) {
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if (UseZba && bits == 32) {
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zext_w(dst, src);
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return;
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}
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if (UseZbb && bits == 16) {
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zext_h(dst, src);
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return;
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}
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if (bits == 8) {
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zext_b(dst, src);
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} else {
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slli(dst, src, XLEN - bits);
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srli(dst, dst, XLEN - bits);
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switch (bits) {
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case 32:
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if (UseZba) {
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zext_w(dst, src);
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return;
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}
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break;
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case 16:
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if (UseZbb) {
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zext_h(dst, src);
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return;
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}
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break;
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case 8:
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if (UseZbb) {
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zext_b(dst, src);
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return;
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}
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break;
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default:
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break;
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}
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slli(dst, src, XLEN - bits);
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srli(dst, dst, XLEN - bits);
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}
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void MacroAssembler::sign_extend(Register dst, Register src, int bits) {
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if (UseZbb) {
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if (bits == 8) {
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sext_b(dst, src);
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switch (bits) {
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case 32:
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sext_w(dst, src);
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return;
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} else if (bits == 16) {
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sext_h(dst, src);
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return;
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}
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}
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if (bits == 32) {
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sext_w(dst, src);
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} else {
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slli(dst, src, XLEN - bits);
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srai(dst, dst, XLEN - bits);
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case 16:
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if (UseZbb) {
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sext_h(dst, src);
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return;
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}
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break;
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case 8:
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if (UseZbb) {
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sext_b(dst, src);
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return;
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}
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break;
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default:
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break;
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}
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slli(dst, src, XLEN - bits);
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srai(dst, dst, XLEN - bits);
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}
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void MacroAssembler::cmp_x2i(Register dst, Register src1, Register src2,
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@ -473,7 +473,11 @@ class MacroAssembler: public Assembler {
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}
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inline void notr(Register Rd, Register Rs) {
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xori(Rd, Rs, -1);
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if (do_compress_zcb(Rd, Rs) && (Rd == Rs)) {
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c_not(Rd);
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} else {
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xori(Rd, Rs, -1);
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}
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}
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inline void neg(Register Rd, Register Rs) {
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@ -489,7 +493,11 @@ class MacroAssembler: public Assembler {
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}
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inline void zext_b(Register Rd, Register Rs) {
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andi(Rd, Rs, 0xFF);
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if (do_compress_zcb(Rd, Rs) && (Rd == Rs)) {
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c_zext_b(Rd);
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} else {
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andi(Rd, Rs, 0xFF);
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}
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}
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inline void seqz(Register Rd, Register Rs) {
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@ -511,7 +519,12 @@ class MacroAssembler: public Assembler {
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// Bit-manipulation extension pseudo instructions
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// zero extend word
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inline void zext_w(Register Rd, Register Rs) {
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add_uw(Rd, Rs, zr);
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assert(UseZba, "must be");
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if (do_compress_zcb(Rd, Rs) && (Rd == Rs)) {
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c_zext_w(Rd);
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} else {
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add_uw(Rd, Rs, zr);
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}
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}
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// Floating-point data-processing pseudo instructions
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@ -110,6 +110,9 @@ class VM_Version : public Abstract_VM_Version {
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// Zic64b Cache blocks must be 64 bytes in size, naturally aligned in the address space.
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// Zihintpause Pause instruction HINT
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||||
//
|
||||
// Zc Code Size Reduction - Additional compressed instructions.
|
||||
// Zcb Simple code-size saving instructions
|
||||
//
|
||||
// Other features and settings
|
||||
// mvendorid Manufactory JEDEC id encoded, ISA vol 2 3.1.2..
|
||||
// marchid Id for microarch. Mvendorid plus marchid uniquely identify the microarch.
|
||||
@ -117,6 +120,8 @@ class VM_Version : public Abstract_VM_Version {
|
||||
// unaligned_access Unaligned memory accesses (unknown, unspported, emulated, slow, firmware, fast)
|
||||
// satp mode SATP bits (number of virtual addr bits) mbare, sv39, sv48, sv57, sv64
|
||||
|
||||
public:
|
||||
|
||||
#define RV_NO_FLAG_BIT (BitsPerWord+1) // nth_bit will return 0 on values larger than BitsPerWord
|
||||
|
||||
// declaration name , extension name, bit pos ,in str, mapped flag)
|
||||
@ -137,6 +142,7 @@ class VM_Version : public Abstract_VM_Version {
|
||||
decl(ext_Zbb , "Zbb" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZbb)) \
|
||||
decl(ext_Zbc , "Zbc" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
|
||||
decl(ext_Zbs , "Zbs" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZbs)) \
|
||||
decl(ext_Zcb , "Zcb" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
|
||||
decl(ext_Zicsr , "Zicsr" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
|
||||
decl(ext_Zifencei , "Zifencei" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
|
||||
decl(ext_Zic64b , "Zic64b" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZic64b)) \
|
||||
|
@ -240,6 +240,8 @@ void VM_Version::rivos_features() {
|
||||
ext_Zbb.enable_feature();
|
||||
ext_Zbs.enable_feature();
|
||||
|
||||
ext_Zcb.enable_feature();
|
||||
|
||||
ext_Zicsr.enable_feature();
|
||||
ext_Zifencei.enable_feature();
|
||||
ext_Zic64b.enable_feature();
|
||||
|
Loading…
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Reference in New Issue
Block a user