8309258: RISC-V: Add riscv_hwprobe syscall
Reviewed-by: fjiang, stuefe, fyang, luhenry
This commit is contained in:
Robbin Ehn
parent
4a9cc8a000
commit
31b6fd775f
src/hotspot
cpu/riscv
os_cpu/linux_riscv
@ -1,6 +1,7 @@
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/*
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* Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2020, 2023, Huawei Technologies Co., Ltd. All rights reserved.
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* Copyright (c) 2023, Rivos Inc. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -30,10 +31,20 @@
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#include "utilities/formatBuffer.hpp"
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#include "utilities/macros.hpp"
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const char* VM_Version::_uarch = "";
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const char* VM_Version::_vm_mode = "";
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#include <ctype.h>
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uint32_t VM_Version::_initial_vector_length = 0;
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#define DEF_RV_FEATURE(NAME, PRETTY, BIT, FSTRING, FLAGF) \
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VM_Version::NAME##RVFeatureValue VM_Version::NAME(PRETTY, BIT, FSTRING);
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RV_FEATURE_FLAGS(DEF_RV_FEATURE)
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#define ADD_RV_FEATURE_IN_LIST(NAME, PRETTY, BIT, FSTRING, FLAGF) \
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&VM_Version::NAME,
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VM_Version::RVFeatureValue* VM_Version::_feature_list[] = {
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RV_FEATURE_FLAGS(ADD_RV_FEATURE_IN_LIST)
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nullptr};
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void VM_Version::initialize() {
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_supports_cx8 = true;
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_supports_atomic_getset4 = true;
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@ -41,13 +52,14 @@ void VM_Version::initialize() {
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_supports_atomic_getset8 = true;
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_supports_atomic_getadd8 = true;
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get_os_cpu_info();
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setup_cpu_available_features();
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// check if satp.mode is supported, currently supports up to SV48(RV64)
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if (get_satp_mode() > VM_SV48) {
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if (satp_mode.value() > VM_SV48 || satp_mode.value() < VM_MBARE) {
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vm_exit_during_initialization(
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err_msg("Unsupported satp mode: %s. Only satp modes up to sv48 are supported for now.",
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_vm_mode));
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err_msg(
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"Unsupported satp mode: SV%d. Only satp modes up to sv48 are supported for now.",
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(int)satp_mode.value()));
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}
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// https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva20-profiles
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@ -165,16 +177,16 @@ void VM_Version::initialize() {
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}
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if (UseRVV) {
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if (!(_features & CPU_V)) {
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if (!ext_V.enabled()) {
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warning("RVV is not supported on this CPU");
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FLAG_SET_DEFAULT(UseRVV, false);
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} else {
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// read vector length from vector CSR vlenb
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_initial_vector_length = get_current_vector_length();
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_initial_vector_length = cpu_vector_length();
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}
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}
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if (UseRVC && !(_features & CPU_C)) {
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if (UseRVC && !ext_C.enabled()) {
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warning("RVC is not supported on this CPU");
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FLAG_SET_DEFAULT(UseRVC, false);
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@ -185,7 +197,11 @@ void VM_Version::initialize() {
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}
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if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
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FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
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if (unaligned_access.value() != MISALIGNED_FAST) {
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FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
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} else {
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FLAG_SET_DEFAULT(AvoidUnalignedAccesses, false);
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}
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}
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if (UseZbb) {
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@ -208,16 +224,6 @@ void VM_Version::initialize() {
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FLAG_SET_DEFAULT(UseBlockZeroing, false);
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}
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char buf[512];
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buf[0] = '\0';
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if (_uarch != nullptr && strcmp(_uarch, "") != 0) snprintf(buf, sizeof(buf), "%s,", _uarch);
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strcat(buf, "rv64");
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#define ADD_FEATURE_IF_SUPPORTED(id, name, bit) if (_features & CPU_##id) strcat(buf, name);
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CPU_FEATURE_FLAGS(ADD_FEATURE_IF_SUPPORTED)
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#undef ADD_FEATURE_IF_SUPPORTED
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_features_string = os::strdup(buf);
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#ifdef COMPILER2
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c2_initialize();
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#endif // COMPILER2
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@ -333,6 +339,6 @@ void VM_Version::initialize_cpu_information(void) {
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_no_of_threads = _no_of_cores;
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_no_of_sockets = _no_of_cores;
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snprintf(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "RISCV64");
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snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "RISCV64 %s", _features_string);
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snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "RISCV64 %s", features_string());
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_initialized = true;
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}
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@ -2,6 +2,7 @@
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* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
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* Copyright (c) 2020, 2023, Huawei Technologies Co., Ltd. All rights reserved.
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* Copyright (c) 2023, Rivos Inc. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -30,55 +31,176 @@
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#include "runtime/abstract_vm_version.hpp"
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#include "runtime/arguments.hpp"
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#include "runtime/globals_extension.hpp"
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#include "utilities/globalDefinitions.hpp"
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#include "utilities/growableArray.hpp"
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#include "utilities/sizes.hpp"
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class RiscvHwprobe;
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class VM_Version : public Abstract_VM_Version {
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friend RiscvHwprobe;
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private:
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class RVFeatureValue {
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const char* const _pretty;
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const bool _feature_string;
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const uint64_t _feature_bit;
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bool _enabled;
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int64_t _value;
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public:
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RVFeatureValue(const char* pretty, int bit_num, bool fstring) :
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_pretty(pretty), _feature_string(fstring), _feature_bit(nth_bit(bit_num)),
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_enabled(false), _value(-1) {
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}
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void enable_feature(int64_t value = 0) {
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_enabled = true;
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_value = value;
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}
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const char* const pretty() { return _pretty; }
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const uint64_t feature_bit() { return _feature_bit; }
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const bool feature_string() { return _feature_string; }
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bool enabled() { return _enabled; }
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int64_t value() { return _value; }
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virtual void update_flag() = 0;
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};
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#define UPDATE_DEFAULT(flag) \
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void update_flag() { \
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assert(enabled(), "Must be."); \
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if (FLAG_IS_DEFAULT(flag)) { \
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FLAG_SET_DEFAULT(flag, true); \
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} \
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} \
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#define NO_UPDATE_DEFAULT \
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void update_flag() {} \
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// Frozen standard extensions
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// I RV64I
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// M Integer Multiplication and Division
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// A Atomic Instructions
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// F Single-Precision Floating-Point
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// D Single-Precision Floating-Point
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// (G = M + A + F + D)
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// Q Quad-Precision Floating-Point
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// C Compressed Instructions
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// H Hypervisor
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//
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// Others, open and non-standard
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// V Vector
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//
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// Cache Management Operations
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// Zicbom Cache Block Management Operations
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// Zicboz Cache Block Zero Operations
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// Zicbop Cache Block Prefetch Operations
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//
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// Bit-manipulation
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// Zba Address generation instructions
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// Zbb Basic bit-manipulation
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// Zbc Carry-less multiplication
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// Zbs Single-bit instructions
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//
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// Zicsr Control and Status Register (CSR) Instructions
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// Zifencei Instruction-Fetch Fence
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// Zic64b Cache blocks must be 64 bytes in size, naturally aligned in the address space.
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// Zihintpause Pause instruction HINT
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//
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// Other features and settings
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// mvendorid Manufactory JEDEC id encoded, ISA vol 2 3.1.2..
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// marchid Id for microarch. Mvendorid plus marchid uniquely identify the microarch.
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// mimpid A unique encoding of the version of the processor implementation.
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// unaligned_access Unaligned memory accesses (unknown, unspported, emulated, slow, firmware, fast)
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// satp mode SATP bits (number of virtual addr bits) mbare, sv39, sv48, sv57, sv64
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#define RV_NO_FLAG_BIT (BitsPerWord+1) // nth_bit will return 0 on values larger than BitsPerWord
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// declaration name , extension name, bit pos ,in str, mapped flag)
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#define RV_FEATURE_FLAGS(decl) \
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decl(ext_I , "i" , ('I' - 'A'), true , NO_UPDATE_DEFAULT) \
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decl(ext_M , "m" , ('M' - 'A'), true , NO_UPDATE_DEFAULT) \
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decl(ext_A , "a" , ('A' - 'A'), true , NO_UPDATE_DEFAULT) \
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decl(ext_F , "f" , ('F' - 'A'), true , NO_UPDATE_DEFAULT) \
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decl(ext_D , "d" , ('D' - 'A'), true , NO_UPDATE_DEFAULT) \
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decl(ext_C , "c" , ('C' - 'A'), true , UPDATE_DEFAULT(UseRVC)) \
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decl(ext_Q , "q" , ('Q' - 'A'), true , NO_UPDATE_DEFAULT) \
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decl(ext_H , "h" , ('H' - 'A'), true , NO_UPDATE_DEFAULT) \
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decl(ext_V , "v" , ('V' - 'A'), true , UPDATE_DEFAULT(UseRVV)) \
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decl(ext_Zicbom , "Zicbom" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZicbom)) \
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decl(ext_Zicboz , "Zicboz" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZicboz)) \
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decl(ext_Zicbop , "Zicbop" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZicbop)) \
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decl(ext_Zba , "Zba" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZba)) \
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decl(ext_Zbb , "Zbb" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZbb)) \
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decl(ext_Zbc , "Zbc" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
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decl(ext_Zbs , "Zbs" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZbs)) \
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decl(ext_Zicsr , "Zicsr" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
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decl(ext_Zifencei , "Zifencei" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
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decl(ext_Zic64b , "Zic64b" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZic64b)) \
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decl(ext_Zihintpause , "Zihintpause" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZihintpause)) \
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decl(mvendorid , "VendorId" , RV_NO_FLAG_BIT, false, NO_UPDATE_DEFAULT) \
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decl(marchid , "ArchId" , RV_NO_FLAG_BIT, false, NO_UPDATE_DEFAULT) \
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decl(mimpid , "ImpId" , RV_NO_FLAG_BIT, false, NO_UPDATE_DEFAULT) \
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decl(unaligned_access, "Unaligned" , RV_NO_FLAG_BIT, false, NO_UPDATE_DEFAULT) \
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decl(satp_mode , "SATP" , RV_NO_FLAG_BIT, false, NO_UPDATE_DEFAULT) \
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#define DECLARE_RV_FEATURE(NAME, PRETTY, BIT, FSTRING, FLAGF) \
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struct NAME##RVFeatureValue : public RVFeatureValue { \
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NAME##RVFeatureValue(const char* pretty, int bit, bool fstring) : \
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RVFeatureValue(pretty, bit, fstring) {} \
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FLAGF; \
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}; \
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static NAME##RVFeatureValue NAME; \
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RV_FEATURE_FLAGS(DECLARE_RV_FEATURE)
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#undef DECLARE_RV_FEATURE
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// VM modes (satp.mode) privileged ISA 1.10
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enum VM_MODE : int {
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VM_NOTSET = -1,
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VM_MBARE = 0,
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VM_SV39 = 39,
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VM_SV48 = 48,
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VM_SV57 = 57,
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VM_SV64 = 64
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};
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static VM_MODE parse_satp_mode(const char* vm_mode);
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// Values from riscv_hwprobe()
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enum UNALIGNED_ACCESS : int {
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MISALIGNED_UNKNOWN = 0,
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MISALIGNED_EMULATED = 1,
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MISALIGNED_SLOW = 2,
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MISALIGNED_FAST = 3,
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MISALIGNED_UNSUPPORTED = 4
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};
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// Null terminated list
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static RVFeatureValue* _feature_list[];
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// Enables features in _feature_list
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static void setup_cpu_available_features();
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// Helper for specific queries
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static void os_aux_features();
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static char* os_uarch_additional_features();
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static void vendor_features();
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// Vendors specific features
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static void rivos_features();
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// Determine vector length iff ext_V/UseRVV
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static uint32_t cpu_vector_length();
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static uint32_t _initial_vector_length;
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#ifdef COMPILER2
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private:
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static void c2_initialize();
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#endif // COMPILER2
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// VM modes (satp.mode) privileged ISA 1.10
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enum VM_MODE {
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VM_MBARE = 0,
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VM_SV39 = 8,
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VM_SV48 = 9,
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VM_SV57 = 10,
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VM_SV64 = 11
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};
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protected:
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static const char* _uarch;
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static const char* _vm_mode;
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static uint32_t _initial_vector_length;
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static void get_os_cpu_info();
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static uint32_t get_current_vector_length();
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static VM_MODE get_satp_mode();
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public:
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public:
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// Initialization
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static void initialize();
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static void initialize_cpu_information();
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constexpr static bool supports_stack_watermark_barrier() { return true; }
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static bool supports_on_spin_wait() { return UseZihintpause; }
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enum Feature_Flag {
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#define CPU_FEATURE_FLAGS(decl) \
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decl(I, "i", 8) \
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decl(M, "m", 12) \
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decl(A, "a", 0) \
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decl(F, "f", 5) \
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decl(D, "d", 3) \
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decl(C, "c", 2) \
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decl(V, "v", 21)
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#define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1 << bit),
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CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
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#undef DECLARE_CPU_FEATURE_FLAG
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};
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static void initialize_cpu_information(void);
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};
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#endif // CPU_RISCV_VM_VERSION_RISCV_HPP
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136
src/hotspot/os_cpu/linux_riscv/riscv_hwprobe.cpp
Normal file
136
src/hotspot/os_cpu/linux_riscv/riscv_hwprobe.cpp
Normal file
@ -0,0 +1,136 @@
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/*
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* Copyright (c) 2023, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2023, Rivos Inc. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#include "precompiled.hpp"
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#include "logging/log.hpp"
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#include "riscv_hwprobe.hpp"
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#include "runtime/os.hpp"
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#include "runtime/vm_version.hpp"
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#include "utilities/debug.hpp"
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#include <sched.h>
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#include <sys/syscall.h>
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#include <unistd.h>
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// Syscall defined in kernel 6.4 and the defines will be in asm/hwprobe.h
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#define RISCV_HWPROBE_KEY_MVENDORID 0
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#define RISCV_HWPROBE_KEY_MARCHID 1
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#define RISCV_HWPROBE_KEY_MIMPID 2
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#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
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#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
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#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
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#define RISCV_HWPROBE_IMA_FD (1 << 0)
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#define RISCV_HWPROBE_IMA_C (1 << 1)
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#define RISCV_HWPROBE_KEY_CPUPERF_0 5
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#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
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#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
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#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0)
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#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0)
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#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
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#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
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#ifndef NR_riscv_hwprobe
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#ifndef NR_arch_specific_syscall
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#define NR_arch_specific_syscall 244
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#endif
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#define NR_riscv_hwprobe (NR_arch_specific_syscall + 14)
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#endif
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struct riscv_hwprobe {
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int64_t key;
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uint64_t value;
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};
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long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pairc,
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size_t cpuc, cpu_set_t *cpus,
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unsigned int flags) {
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return syscall(NR_riscv_hwprobe, pairs, pairc, cpuc, cpus, 0 /* flags*/);
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}
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static bool rw_hwprobe_completed = false;
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static struct riscv_hwprobe query[] = {{RISCV_HWPROBE_KEY_MVENDORID, 0},
|
||||
{RISCV_HWPROBE_KEY_MARCHID, 0},
|
||||
{RISCV_HWPROBE_KEY_MIMPID, 0},
|
||||
{RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0},
|
||||
{RISCV_HWPROBE_KEY_IMA_EXT_0, 0},
|
||||
{RISCV_HWPROBE_KEY_CPUPERF_0, 0}};
|
||||
|
||||
bool RiscvHwprobe::probe_features() {
|
||||
assert(!rw_hwprobe_completed, "Called twice.");
|
||||
int ret = sys_riscv_hwprobe(&query[0], sizeof(query) / sizeof(query[0]), 0, nullptr, 0);
|
||||
rw_hwprobe_completed = true;
|
||||
if (ret != 0) {
|
||||
log_debug(os, cpu)("riscv_hwprobe unsupported");
|
||||
return false;
|
||||
}
|
||||
log_debug(os, cpu)("riscv_hwprobe supported");
|
||||
add_features_from_query_result();
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool is_valid(int64_t key) {
|
||||
return query[key].key != -1;
|
||||
}
|
||||
|
||||
static bool is_set(int64_t key, uint64_t value_mask) {
|
||||
if (is_valid(key)) {
|
||||
return query[key].value & value_mask != 0;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
void RiscvHwprobe::add_features_from_query_result() {
|
||||
assert(rw_hwprobe_completed, "hwprobe not init yet.");
|
||||
|
||||
if (is_valid(RISCV_HWPROBE_KEY_MVENDORID)) {
|
||||
VM_Version::mvendorid.enable_feature(query[RISCV_HWPROBE_KEY_MVENDORID].value);
|
||||
}
|
||||
if (is_valid(RISCV_HWPROBE_KEY_MARCHID)) {
|
||||
VM_Version::marchid.enable_feature(query[RISCV_HWPROBE_KEY_MARCHID].value);
|
||||
}
|
||||
if (is_valid(RISCV_HWPROBE_KEY_MIMPID)) {
|
||||
VM_Version::mimpid.enable_feature(query[RISCV_HWPROBE_KEY_MIMPID].value);
|
||||
}
|
||||
if (is_set(RISCV_HWPROBE_KEY_BASE_BEHAVIOR, RISCV_HWPROBE_BASE_BEHAVIOR_IMA)) {
|
||||
VM_Version::ext_I.enable_feature();
|
||||
VM_Version::ext_M.enable_feature();
|
||||
VM_Version::ext_A.enable_feature();
|
||||
}
|
||||
if (is_set(RISCV_HWPROBE_KEY_IMA_EXT_0, RISCV_HWPROBE_IMA_FD)) {
|
||||
VM_Version::ext_F.enable_feature();
|
||||
VM_Version::ext_D.enable_feature();
|
||||
}
|
||||
if (is_set(RISCV_HWPROBE_KEY_IMA_EXT_0, RISCV_HWPROBE_IMA_C)) {
|
||||
VM_Version::ext_C.enable_feature();
|
||||
}
|
||||
if (is_valid(RISCV_HWPROBE_KEY_CPUPERF_0)) {
|
||||
VM_Version::unaligned_access.enable_feature(
|
||||
query[RISCV_HWPROBE_KEY_CPUPERF_0].value & RISCV_HWPROBE_MISALIGNED_MASK);
|
||||
}
|
||||
}
|
||||
39
src/hotspot/os_cpu/linux_riscv/riscv_hwprobe.hpp
Normal file
39
src/hotspot/os_cpu/linux_riscv/riscv_hwprobe.hpp
Normal file
@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (c) 2023, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2023, Rivos Inc. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 only, as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This code is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* version 2 for more details (a copy is included in the LICENSE file that
|
||||
* accompanied this code).
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License version
|
||||
* 2 along with this work; if not, write to the Free Software Foundation,
|
||||
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
|
||||
* or visit www.oracle.com if you need additional information or have any
|
||||
* questions.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef OS_LINUX_RISCV_HWPROBE_LINUX_HPP
|
||||
#define OS_LINUX_RISCV_HWPROBE_LINUX_HPP
|
||||
|
||||
#include "memory/allStatic.hpp"
|
||||
#include "runtime/vm_version.hpp"
|
||||
#include "utilities/growableArray.hpp"
|
||||
|
||||
class RiscvHwprobe: public AllStatic {
|
||||
static void add_features_from_query_result();
|
||||
public:
|
||||
static bool probe_features();
|
||||
};
|
||||
|
||||
#endif // OS_LINUX_RISCV_HWPROBE_LINUX_HPP
|
||||
@ -1,6 +1,7 @@
|
||||
/*
|
||||
* Copyright (c) 2006, 2023, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2021, Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2023, Rivos Inc. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -25,39 +26,50 @@
|
||||
|
||||
#include "precompiled.hpp"
|
||||
#include "asm/register.hpp"
|
||||
#include "logging/log.hpp"
|
||||
#include "riscv_hwprobe.hpp"
|
||||
#include "runtime/os.hpp"
|
||||
#include "runtime/os.inline.hpp"
|
||||
#include "runtime/vm_version.hpp"
|
||||
|
||||
#include <asm/hwcap.h>
|
||||
#include <ctype.h>
|
||||
#include <sys/auxv.h>
|
||||
|
||||
#ifndef HWCAP_ISA_I
|
||||
#define HWCAP_ISA_I (1 << ('I' - 'A'))
|
||||
#define HWCAP_ISA_I nth_bit('I' - 'A')
|
||||
#endif
|
||||
|
||||
#ifndef HWCAP_ISA_M
|
||||
#define HWCAP_ISA_M (1 << ('M' - 'A'))
|
||||
#define HWCAP_ISA_M nth_bit('M' - 'A')
|
||||
#endif
|
||||
|
||||
#ifndef HWCAP_ISA_A
|
||||
#define HWCAP_ISA_A (1 << ('A' - 'A'))
|
||||
#define HWCAP_ISA_A nth_bit('A' - 'A')
|
||||
#endif
|
||||
|
||||
#ifndef HWCAP_ISA_F
|
||||
#define HWCAP_ISA_F (1 << ('F' - 'A'))
|
||||
#define HWCAP_ISA_F nth_bit('F' - 'A')
|
||||
#endif
|
||||
|
||||
#ifndef HWCAP_ISA_D
|
||||
#define HWCAP_ISA_D (1 << ('D' - 'A'))
|
||||
#define HWCAP_ISA_D nth_bit('D' - 'A')
|
||||
#endif
|
||||
|
||||
#ifndef HWCAP_ISA_C
|
||||
#define HWCAP_ISA_C (1 << ('C' - 'A'))
|
||||
#define HWCAP_ISA_C nth_bit('C' - 'A')
|
||||
#endif
|
||||
|
||||
#ifndef HWCAP_ISA_Q
|
||||
#define HWCAP_ISA_Q nth_bit('Q' - 'A')
|
||||
#endif
|
||||
|
||||
#ifndef HWCAP_ISA_H
|
||||
#define HWCAP_ISA_H nth_bit('H' - 'A')
|
||||
#endif
|
||||
|
||||
#ifndef HWCAP_ISA_V
|
||||
#define HWCAP_ISA_V (1 << ('V' - 'A'))
|
||||
#define HWCAP_ISA_V nth_bit('V' - 'A')
|
||||
#endif
|
||||
|
||||
#define read_csr(csr) \
|
||||
@ -70,68 +82,173 @@
|
||||
__v; \
|
||||
})
|
||||
|
||||
uint32_t VM_Version::get_current_vector_length() {
|
||||
assert(_features & CPU_V, "should not call this");
|
||||
uint32_t VM_Version::cpu_vector_length() {
|
||||
assert(ext_V.enabled(), "should not call this");
|
||||
return (uint32_t)read_csr(CSR_VLENB);
|
||||
}
|
||||
|
||||
VM_Version::VM_MODE VM_Version::get_satp_mode() {
|
||||
if (!strcmp(_vm_mode, "sv39")) {
|
||||
void VM_Version::setup_cpu_available_features() {
|
||||
|
||||
assert(ext_I.feature_bit() == HWCAP_ISA_I, "Bit for I must follow Linux HWCAP");
|
||||
assert(ext_M.feature_bit() == HWCAP_ISA_M, "Bit for M must follow Linux HWCAP");
|
||||
assert(ext_A.feature_bit() == HWCAP_ISA_A, "Bit for A must follow Linux HWCAP");
|
||||
assert(ext_F.feature_bit() == HWCAP_ISA_F, "Bit for F must follow Linux HWCAP");
|
||||
assert(ext_D.feature_bit() == HWCAP_ISA_D, "Bit for D must follow Linux HWCAP");
|
||||
assert(ext_C.feature_bit() == HWCAP_ISA_C, "Bit for C must follow Linux HWCAP");
|
||||
assert(ext_Q.feature_bit() == HWCAP_ISA_Q, "Bit for Q must follow Linux HWCAP");
|
||||
assert(ext_H.feature_bit() == HWCAP_ISA_H, "Bit for H must follow Linux HWCAP");
|
||||
assert(ext_V.feature_bit() == HWCAP_ISA_V, "Bit for V must follow Linux HWCAP");
|
||||
|
||||
if (!RiscvHwprobe::probe_features()) {
|
||||
os_aux_features();
|
||||
}
|
||||
char* uarch = os_uarch_additional_features();
|
||||
vendor_features();
|
||||
|
||||
char buf[1024] = {};
|
||||
if (uarch != nullptr && strcmp(uarch, "") != 0) {
|
||||
// Use at max half the buffer.
|
||||
snprintf(buf, sizeof(buf)/2, "%s,", uarch);
|
||||
}
|
||||
os::free((void*) uarch);
|
||||
strcat(buf, "rv64");
|
||||
int i = 0;
|
||||
while (_feature_list[i] != nullptr) {
|
||||
if (_feature_list[i]->enabled()) {
|
||||
log_debug(os, cpu)("Enabled RV64 feature \"%s\" (%ld)",
|
||||
_feature_list[i]->pretty(),
|
||||
_feature_list[i]->value());
|
||||
// The feature string
|
||||
if (_feature_list[i]->feature_string()) {
|
||||
const char* tmp = _feature_list[i]->pretty();
|
||||
if (strlen(tmp) == 1) {
|
||||
strcat(buf, tmp);
|
||||
} else {
|
||||
// Feature string is expected to be lower case.
|
||||
// Turn Zxxx into zxxx
|
||||
char prebuf[3] = {};
|
||||
assert(strlen(tmp) > 1, "Must be");
|
||||
prebuf[0] = '_';
|
||||
prebuf[1] = (char)tolower(tmp[0]);
|
||||
strcat(buf, prebuf);
|
||||
strcat(buf, &tmp[1]);
|
||||
}
|
||||
}
|
||||
// Feature bit
|
||||
if (_feature_list[i]->feature_bit() != 0) {
|
||||
_features |= _feature_list[i]->feature_bit();
|
||||
}
|
||||
// Change flag default
|
||||
_feature_list[i]->update_flag();
|
||||
}
|
||||
i++;
|
||||
}
|
||||
|
||||
_features_string = os::strdup(buf);
|
||||
}
|
||||
|
||||
void VM_Version::os_aux_features() {
|
||||
uint64_t auxv = getauxval(AT_HWCAP);
|
||||
int i = 0;
|
||||
while (_feature_list[i] != nullptr) {
|
||||
if ((_feature_list[i]->feature_bit() & auxv) != 0) {
|
||||
_feature_list[i]->enable_feature();
|
||||
}
|
||||
i++;
|
||||
}
|
||||
}
|
||||
|
||||
VM_Version::VM_MODE VM_Version::parse_satp_mode(const char* vm_mode) {
|
||||
if (!strcmp(vm_mode, "sv39")) {
|
||||
return VM_SV39;
|
||||
} else if (!strcmp(_vm_mode, "sv48")) {
|
||||
} else if (!strcmp(vm_mode, "sv48")) {
|
||||
return VM_SV48;
|
||||
} else if (!strcmp(_vm_mode, "sv57")) {
|
||||
} else if (!strcmp(vm_mode, "sv57")) {
|
||||
return VM_SV57;
|
||||
} else if (!strcmp(_vm_mode, "sv64")) {
|
||||
} else if (!strcmp(vm_mode, "sv64")) {
|
||||
return VM_SV64;
|
||||
} else {
|
||||
return VM_MBARE;
|
||||
}
|
||||
}
|
||||
|
||||
void VM_Version::get_os_cpu_info() {
|
||||
char* VM_Version::os_uarch_additional_features() {
|
||||
char* ret = nullptr;
|
||||
VM_MODE mode = VM_NOTSET;
|
||||
|
||||
uint64_t auxv = getauxval(AT_HWCAP);
|
||||
FILE *f = fopen("/proc/cpuinfo", "r");
|
||||
if (f == nullptr) {
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
static_assert(CPU_I == HWCAP_ISA_I, "Flag CPU_I must follow Linux HWCAP");
|
||||
static_assert(CPU_M == HWCAP_ISA_M, "Flag CPU_M must follow Linux HWCAP");
|
||||
static_assert(CPU_A == HWCAP_ISA_A, "Flag CPU_A must follow Linux HWCAP");
|
||||
static_assert(CPU_F == HWCAP_ISA_F, "Flag CPU_F must follow Linux HWCAP");
|
||||
static_assert(CPU_D == HWCAP_ISA_D, "Flag CPU_D must follow Linux HWCAP");
|
||||
static_assert(CPU_C == HWCAP_ISA_C, "Flag CPU_C must follow Linux HWCAP");
|
||||
static_assert(CPU_V == HWCAP_ISA_V, "Flag CPU_V must follow Linux HWCAP");
|
||||
|
||||
// RISC-V has four bit-manipulation ISA-extensions: Zba/Zbb/Zbc/Zbs.
|
||||
// Availability for those extensions could not be queried from HWCAP.
|
||||
// TODO: Add proper detection for those extensions.
|
||||
_features = auxv & (
|
||||
HWCAP_ISA_I |
|
||||
HWCAP_ISA_M |
|
||||
HWCAP_ISA_A |
|
||||
HWCAP_ISA_F |
|
||||
HWCAP_ISA_D |
|
||||
HWCAP_ISA_C |
|
||||
HWCAP_ISA_V);
|
||||
|
||||
if (FILE *f = fopen("/proc/cpuinfo", "r")) {
|
||||
char buf[512], *p;
|
||||
while (fgets(buf, sizeof (buf), f) != nullptr) {
|
||||
if ((p = strchr(buf, ':')) != nullptr) {
|
||||
char buf[512], *p;
|
||||
while (fgets(buf, sizeof (buf), f) != nullptr &&
|
||||
(mode == VM_NOTSET || ret == nullptr)) {
|
||||
if ((p = strchr(buf, ':')) != nullptr) {
|
||||
if (mode == VM_NOTSET) {
|
||||
if (strncmp(buf, "mmu", sizeof "mmu" - 1) == 0) {
|
||||
if (_vm_mode[0] != '\0') {
|
||||
continue;
|
||||
}
|
||||
char* vm_mode = os::strdup(p + 2);
|
||||
vm_mode[strcspn(vm_mode, "\n")] = '\0';
|
||||
_vm_mode = vm_mode;
|
||||
} else if (strncmp(buf, "uarch", sizeof "uarch" - 1) == 0) {
|
||||
char* uarch = os::strdup(p + 2);
|
||||
uarch[strcspn(uarch, "\n")] = '\0';
|
||||
_uarch = uarch;
|
||||
break;
|
||||
mode = VM_Version::parse_satp_mode(p);
|
||||
}
|
||||
}
|
||||
if (ret == nullptr) {
|
||||
if (strncmp(buf, "uarch", sizeof "uarch" - 1) == 0) {
|
||||
ret = os::strdup(p + 2);
|
||||
ret[strcspn(ret, "\n")] = '\0';
|
||||
}
|
||||
}
|
||||
}
|
||||
fclose(f);
|
||||
}
|
||||
if (mode == VM_NOTSET) {
|
||||
mode = VM_MBARE;
|
||||
}
|
||||
fclose(f);
|
||||
satp_mode.enable_feature(mode);
|
||||
return ret;
|
||||
}
|
||||
|
||||
void VM_Version::vendor_features() {
|
||||
// JEDEC encoded as ((bank - 1) << 7) | (0x7f & JEDEC)
|
||||
static constexpr int RIVOS_MVENDORID = 0x6cf; // JEDEC: 0x4f, Bank: 14
|
||||
|
||||
if (!mvendorid.enabled()) {
|
||||
return;
|
||||
}
|
||||
switch (mvendorid.value()) {
|
||||
case RIVOS_MVENDORID:
|
||||
rivos_features();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void VM_Version::rivos_features() {
|
||||
// Enable common features not dependent on marchid/mimpid.
|
||||
ext_I.enable_feature();
|
||||
ext_M.enable_feature();
|
||||
ext_A.enable_feature();
|
||||
ext_F.enable_feature();
|
||||
ext_D.enable_feature();
|
||||
ext_C.enable_feature();
|
||||
ext_H.enable_feature();
|
||||
ext_V.enable_feature();
|
||||
|
||||
ext_Zicbom.enable_feature();
|
||||
ext_Zicboz.enable_feature();
|
||||
ext_Zicbop.enable_feature();
|
||||
|
||||
ext_Zba.enable_feature();
|
||||
ext_Zbb.enable_feature();
|
||||
ext_Zbs.enable_feature();
|
||||
|
||||
ext_Zicsr.enable_feature();
|
||||
ext_Zifencei.enable_feature();
|
||||
ext_Zic64b.enable_feature();
|
||||
ext_Zihintpause.enable_feature();
|
||||
|
||||
unaligned_access.enable_feature(MISALIGNED_FAST);
|
||||
satp_mode.enable_feature(VM_SV48);
|
||||
|
||||
// Features dependent on march/mimpid.
|
||||
// I.e. march.value() and mimplid.value()
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user