8179527: Implement intrinsic code for reverseBytes with load/store
Reviewed-by: simonis, mdoerr
This commit is contained in:
Michihiro Horie
Martin Doerr
parent
f2b486212e
commit
3312fc717b
@ -376,10 +376,12 @@ class Assembler : public AbstractAssembler {
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STWX_OPCODE = (31u << OPCODE_SHIFT | 151u << 1),
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STWU_OPCODE = (37u << OPCODE_SHIFT),
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STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1),
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STWBRX_OPCODE = (31u << OPCODE_SHIFT | 662u << 1),
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STH_OPCODE = (44u << OPCODE_SHIFT),
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STHX_OPCODE = (31u << OPCODE_SHIFT | 407u << 1),
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STHU_OPCODE = (45u << OPCODE_SHIFT),
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STHBRX_OPCODE = (31u << OPCODE_SHIFT | 918u << 1),
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STB_OPCODE = (38u << OPCODE_SHIFT),
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STBX_OPCODE = (31u << OPCODE_SHIFT | 215u << 1),
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@ -401,11 +403,13 @@ class Assembler : public AbstractAssembler {
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LD_OPCODE = (58u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM
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LDU_OPCODE = (58u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM
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LDX_OPCODE = (31u << OPCODE_SHIFT | 21u << XO_21_30_SHIFT), // X-FORM
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LDBRX_OPCODE = (31u << OPCODE_SHIFT | 532u << 1), // X-FORM
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STD_OPCODE = (62u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM
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STDU_OPCODE = (62u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM
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STDUX_OPCODE = (31u << OPCODE_SHIFT | 181u << 1), // X-FORM
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STDUX_OPCODE = (31u << OPCODE_SHIFT | 181u << 1), // X-FORM
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STDX_OPCODE = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM
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STDBRX_OPCODE = (31u << OPCODE_SHIFT | 660u << 1), // X-FORM
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RLDICR_OPCODE = (30u << OPCODE_SHIFT | 1u << XO_27_29_SHIFT), // MD-FORM
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RLDICL_OPCODE = (30u << OPCODE_SHIFT | 0u << XO_27_29_SHIFT), // MD-FORM
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@ -1552,6 +1556,9 @@ class Assembler : public AbstractAssembler {
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inline void ld( Register d, int si16, Register s1);
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inline void ldu( Register d, int si16, Register s1);
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// 8 bytes reversed
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inline void ldbrx( Register d, Register s1, Register s2);
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// For convenience. Load pointer into d from b+s1.
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inline void ld_ptr(Register d, int b, Register s1);
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DEBUG_ONLY(inline void ld_ptr(Register d, ByteSize b, Register s1);)
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@ -1560,10 +1567,12 @@ class Assembler : public AbstractAssembler {
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inline void stwx( Register d, Register s1, Register s2);
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inline void stw( Register d, int si16, Register s1);
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inline void stwu( Register d, int si16, Register s1);
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inline void stwbrx( Register d, Register s1, Register s2);
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inline void sthx( Register d, Register s1, Register s2);
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inline void sth( Register d, int si16, Register s1);
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inline void sthu( Register d, int si16, Register s1);
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inline void sthbrx( Register d, Register s1, Register s2);
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inline void stbx( Register d, Register s1, Register s2);
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inline void stb( Register d, int si16, Register s1);
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@ -1573,6 +1582,7 @@ class Assembler : public AbstractAssembler {
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inline void std( Register d, int si16, Register s1);
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inline void stdu( Register d, int si16, Register s1);
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inline void stdux(Register s, Register a, Register b);
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inline void stdbrx( Register d, Register s1, Register s2);
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inline void st_ptr(Register d, int si16, Register s1);
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DEBUG_ONLY(inline void st_ptr(Register d, ByteSize b, Register s1);)
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@ -2182,14 +2192,18 @@ class Assembler : public AbstractAssembler {
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inline void lbz( Register d, int si16);
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inline void ldx( Register d, Register s2);
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inline void ld( Register d, int si16);
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inline void ldbrx(Register d, Register s2);
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inline void stwx( Register d, Register s2);
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inline void stw( Register d, int si16);
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inline void stwbrx( Register d, Register s2);
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inline void sthx( Register d, Register s2);
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inline void sth( Register d, int si16);
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inline void sthbrx( Register d, Register s2);
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inline void stbx( Register d, Register s2);
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inline void stb( Register d, int si16);
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inline void stdx( Register d, Register s2);
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inline void std( Register d, int si16);
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inline void stdbrx( Register d, Register s2);
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// PPC 2, section 3.2.1 Instruction Cache Instructions
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inline void icbi( Register s2);
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@ -327,6 +327,7 @@ inline void Assembler::lbzu( Register d, int si16, Register s1) { assert(d !=
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inline void Assembler::ld( Register d, int si16, Register s1) { emit_int32(LD_OPCODE | rt(d) | ds(si16) | ra0mem(s1));}
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inline void Assembler::ldx( Register d, Register s1, Register s2) { emit_int32(LDX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
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inline void Assembler::ldu( Register d, int si16, Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LDU_OPCODE | rt(d) | ds(si16) | rta0mem(s1));}
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inline void Assembler::ldbrx( Register d, Register s1, Register s2) { emit_int32(LDBRX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
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inline void Assembler::ld_ptr(Register d, int b, Register s1) { ld(d, b, s1); }
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DEBUG_ONLY(inline void Assembler::ld_ptr(Register d, ByteSize b, Register s1) { ld(d, in_bytes(b), s1); })
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@ -335,10 +336,12 @@ DEBUG_ONLY(inline void Assembler::ld_ptr(Register d, ByteSize b, Register s1) {
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inline void Assembler::stwx( Register d, Register s1, Register s2) { emit_int32(STWX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
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inline void Assembler::stw( Register d, int si16, Register s1) { emit_int32(STW_OPCODE | rs(d) | d1(si16) | ra0mem(s1));}
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inline void Assembler::stwu( Register d, int si16, Register s1) { emit_int32(STWU_OPCODE | rs(d) | d1(si16) | rta0mem(s1));}
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inline void Assembler::stwbrx( Register d, Register s1, Register s2) { emit_int32(STWBRX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
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inline void Assembler::sthx( Register d, Register s1, Register s2) { emit_int32(STHX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
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inline void Assembler::sth( Register d, int si16, Register s1) { emit_int32(STH_OPCODE | rs(d) | d1(si16) | ra0mem(s1));}
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inline void Assembler::sthu( Register d, int si16, Register s1) { emit_int32(STHU_OPCODE | rs(d) | d1(si16) | rta0mem(s1));}
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inline void Assembler::sthbrx( Register d, Register s1, Register s2) { emit_int32(STHBRX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
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inline void Assembler::stbx( Register d, Register s1, Register s2) { emit_int32(STBX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
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inline void Assembler::stb( Register d, int si16, Register s1) { emit_int32(STB_OPCODE | rs(d) | d1(si16) | ra0mem(s1));}
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@ -348,6 +351,7 @@ inline void Assembler::std( Register d, int si16, Register s1) { emit_int32(
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inline void Assembler::stdx( Register d, Register s1, Register s2) { emit_int32(STDX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
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inline void Assembler::stdu( Register d, int si16, Register s1) { emit_int32(STDU_OPCODE | rs(d) | ds(si16) | rta0mem(s1));}
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inline void Assembler::stdux(Register s, Register a, Register b) { emit_int32(STDUX_OPCODE| rs(s) | rta0mem(a) | rb(b));}
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inline void Assembler::stdbrx( Register d, Register s1, Register s2) { emit_int32(STDBRX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
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inline void Assembler::st_ptr(Register d, int b, Register s1) { std(d, b, s1); }
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DEBUG_ONLY(inline void Assembler::st_ptr(Register d, ByteSize b, Register s1) { std(d, in_bytes(b), s1); })
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@ -944,14 +948,18 @@ inline void Assembler::lbzx( Register d, Register s2) { emit_int32( LBZX_OPCODE
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inline void Assembler::lbz( Register d, int si16 ) { emit_int32( LBZ_OPCODE | rt(d) | d1(si16));}
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inline void Assembler::ld( Register d, int si16 ) { emit_int32( LD_OPCODE | rt(d) | ds(si16));}
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inline void Assembler::ldx( Register d, Register s2) { emit_int32( LDX_OPCODE | rt(d) | rb(s2));}
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inline void Assembler::ldbrx(Register d, Register s2) { emit_int32( LDBRX_OPCODE| rt(d) | rb(s2));}
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inline void Assembler::stwx( Register d, Register s2) { emit_int32( STWX_OPCODE | rs(d) | rb(s2));}
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inline void Assembler::stw( Register d, int si16 ) { emit_int32( STW_OPCODE | rs(d) | d1(si16));}
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inline void Assembler::stwbrx(Register d, Register s2){ emit_int32(STWBRX_OPCODE| rs(d) | rb(s2));}
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inline void Assembler::sthx( Register d, Register s2) { emit_int32( STHX_OPCODE | rs(d) | rb(s2));}
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inline void Assembler::sth( Register d, int si16 ) { emit_int32( STH_OPCODE | rs(d) | d1(si16));}
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inline void Assembler::sthbrx(Register d, Register s2){ emit_int32(STHBRX_OPCODE| rs(d) | rb(s2));}
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inline void Assembler::stbx( Register d, Register s2) { emit_int32( STBX_OPCODE | rs(d) | rb(s2));}
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inline void Assembler::stb( Register d, int si16 ) { emit_int32( STB_OPCODE | rs(d) | d1(si16));}
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inline void Assembler::std( Register d, int si16 ) { emit_int32( STD_OPCODE | rs(d) | ds(si16));}
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inline void Assembler::stdx( Register d, Register s2) { emit_int32( STDX_OPCODE | rs(d) | rb(s2));}
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inline void Assembler::stdbrx(Register d, Register s2){ emit_int32(STDBRX_OPCODE| rs(d) | rb(s2));}
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// ra0 version
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inline void Assembler::icbi( Register s2) { emit_int32( ICBI_OPCODE | rb(s2) ); }
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@ -5842,6 +5842,16 @@ instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
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ins_pipe(pipe_class_default);
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%}
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instruct rldicl(iRegLdst dst, iRegLsrc src, immI16 shift, immI16 mask_begin) %{
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effect(DEF dst, USE src, USE shift, USE mask_begin);
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size(4);
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ins_encode %{
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__ rldicl($dst$$Register, $src$$Register, $shift$$constant, $mask_begin$$constant);
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%}
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ins_pipe(pipe_class_default);
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%}
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// Needed to postalloc expand loadConN: ConN is loaded as ConI
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// leaving the upper 32 bits with sign-extension bits.
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// This clears these bits: dst = src & 0xFFFFFFFF.
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@ -10519,6 +10529,16 @@ instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
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ins_pipe(pipe_class_default);
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%}
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instruct extsh(iRegIdst dst, iRegIsrc src) %{
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effect(DEF dst, USE src);
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size(4);
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ins_encode %{
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__ extsh($dst$$Register, $src$$Register);
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%}
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ins_pipe(pipe_class_default);
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%}
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// LShiftI 16 + RShiftI 16 converts short to int.
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instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
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match(Set dst (RShiftI (LShiftI src amount) amount));
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@ -12682,8 +12702,7 @@ instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
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// Just slightly faster than java implementation.
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instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
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match(Set dst (ReverseBytesI src));
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predicate(UseCountLeadingZerosInstructionsPPC64);
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ins_cost(DEFAULT_COST);
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ins_cost(7*DEFAULT_COST);
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expand %{
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immI16 imm24 %{ (int) 24 %}
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@ -12705,6 +12724,172 @@ instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
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%}
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%}
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instruct bytes_reverse_long_Ex(iRegLdst dst, iRegLsrc src) %{
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match(Set dst (ReverseBytesL src));
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ins_cost(15*DEFAULT_COST);
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expand %{
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immI16 imm56 %{ (int) 56 %}
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immI16 imm48 %{ (int) 48 %}
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immI16 imm40 %{ (int) 40 %}
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immI16 imm32 %{ (int) 32 %}
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immI16 imm24 %{ (int) 24 %}
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immI16 imm16 %{ (int) 16 %}
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immI16 imm8 %{ (int) 8 %}
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immI16 imm0 %{ (int) 0 %}
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iRegLdst tmpL1;
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iRegLdst tmpL2;
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iRegLdst tmpL3;
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iRegLdst tmpL4;
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iRegLdst tmpL5;
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iRegLdst tmpL6;
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// src : |a|b|c|d|e|f|g|h|
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rldicl(tmpL1, src, imm8, imm24); // tmpL1 : | | | |e|f|g|h|a|
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rldicl(tmpL2, tmpL1, imm32, imm24); // tmpL2 : | | | |a| | | |e|
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rldicl(tmpL3, tmpL2, imm32, imm0); // tmpL3 : | | | |e| | | |a|
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rldicl(tmpL1, src, imm16, imm24); // tmpL1 : | | | |f|g|h|a|b|
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rldicl(tmpL2, tmpL1, imm32, imm24); // tmpL2 : | | | |b| | | |f|
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rldicl(tmpL4, tmpL2, imm40, imm0); // tmpL4 : | | |f| | | |b| |
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orL_reg_reg(tmpL5, tmpL3, tmpL4); // tmpL5 : | | |f|e| | |b|a|
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rldicl(tmpL1, src, imm24, imm24); // tmpL1 : | | | |g|h|a|b|c|
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rldicl(tmpL2, tmpL1, imm32, imm24); // tmpL2 : | | | |c| | | |g|
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rldicl(tmpL3, tmpL2, imm48, imm0); // tmpL3 : | |g| | | |c| | |
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rldicl(tmpL1, src, imm32, imm24); // tmpL1 : | | | |h|a|b|c|d|
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rldicl(tmpL2, tmpL1, imm32, imm24); // tmpL2 : | | | |d| | | |h|
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rldicl(tmpL4, tmpL2, imm56, imm0); // tmpL4 : |h| | | |d| | | |
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orL_reg_reg(tmpL6, tmpL3, tmpL4); // tmpL6 : |h|g| | |d|c| | |
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orL_reg_reg(dst, tmpL5, tmpL6); // dst : |h|g|f|e|d|c|b|a|
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%}
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%}
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instruct bytes_reverse_ushort_Ex(iRegIdst dst, iRegIsrc src) %{
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match(Set dst (ReverseBytesUS src));
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ins_cost(2*DEFAULT_COST);
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expand %{
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immI16 imm16 %{ (int) 16 %}
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immI16 imm8 %{ (int) 8 %}
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urShiftI_reg_imm(dst, src, imm8);
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insrwi(dst, src, imm16, imm8);
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%}
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%}
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instruct bytes_reverse_short_Ex(iRegIdst dst, iRegIsrc src) %{
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match(Set dst (ReverseBytesS src));
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ins_cost(3*DEFAULT_COST);
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expand %{
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immI16 imm16 %{ (int) 16 %}
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immI16 imm8 %{ (int) 8 %}
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iRegLdst tmpI1;
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urShiftI_reg_imm(tmpI1, src, imm8);
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insrwi(tmpI1, src, imm16, imm8);
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extsh(dst, tmpI1);
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%}
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%}
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// Load Integer reversed byte order
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instruct loadI_reversed(iRegIdst dst, indirect mem) %{
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match(Set dst (ReverseBytesI (LoadI mem)));
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ins_cost(MEMORY_REF_COST);
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size(4);
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ins_encode %{
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__ lwbrx($dst$$Register, $mem$$Register);
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%}
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ins_pipe(pipe_class_default);
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%}
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// Load Long - aligned and reversed
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instruct loadL_reversed(iRegLdst dst, indirect mem) %{
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match(Set dst (ReverseBytesL (LoadL mem)));
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predicate(VM_Version::has_ldbrx());
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ins_cost(MEMORY_REF_COST);
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size(4);
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ins_encode %{
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__ ldbrx($dst$$Register, $mem$$Register);
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%}
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ins_pipe(pipe_class_default);
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%}
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// Load unsigned short / char reversed byte order
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instruct loadUS_reversed(iRegIdst dst, indirect mem) %{
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match(Set dst (ReverseBytesUS (LoadUS mem)));
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ins_cost(MEMORY_REF_COST);
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size(4);
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ins_encode %{
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__ lhbrx($dst$$Register, $mem$$Register);
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%}
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ins_pipe(pipe_class_default);
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%}
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// Load short reversed byte order
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instruct loadS_reversed(iRegIdst dst, indirect mem) %{
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match(Set dst (ReverseBytesS (LoadS mem)));
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ins_cost(MEMORY_REF_COST + DEFAULT_COST);
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size(8);
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ins_encode %{
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__ lhbrx($dst$$Register, $mem$$Register);
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__ extsh($dst$$Register, $dst$$Register);
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%}
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ins_pipe(pipe_class_default);
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%}
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// Store Integer reversed byte order
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instruct storeI_reversed(iRegIsrc src, indirect mem) %{
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match(Set mem (StoreI mem (ReverseBytesI src)));
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ins_cost(MEMORY_REF_COST);
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size(4);
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ins_encode %{
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__ stwbrx($src$$Register, $mem$$Register);
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%}
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ins_pipe(pipe_class_default);
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%}
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// Store Long reversed byte order
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instruct storeL_reversed(iRegLsrc src, indirect mem) %{
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match(Set mem (StoreL mem (ReverseBytesL src)));
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predicate(VM_Version::has_stdbrx());
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ins_cost(MEMORY_REF_COST);
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size(4);
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ins_encode %{
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__ stdbrx($src$$Register, $mem$$Register);
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%}
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ins_pipe(pipe_class_default);
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%}
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// Store unsigned short / char reversed byte order
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instruct storeUS_reversed(iRegIsrc src, indirect mem) %{
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match(Set mem (StoreC mem (ReverseBytesUS src)));
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ins_cost(MEMORY_REF_COST);
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size(4);
|
||||
ins_encode %{
|
||||
__ sthbrx($src$$Register, $mem$$Register);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
// Store short reversed byte order
|
||||
instruct storeS_reversed(iRegIsrc src, indirect mem) %{
|
||||
match(Set mem (StoreC mem (ReverseBytesS src)));
|
||||
ins_cost(MEMORY_REF_COST);
|
||||
|
||||
size(4);
|
||||
ins_encode %{
|
||||
__ sthbrx($src$$Register, $mem$$Register);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
//---------- Replicate Vector Instructions ------------------------------------
|
||||
|
||||
// Insrdi does replicate if src == dst.
|
||||
|
||||
@ -111,7 +111,7 @@ void VM_Version::initialize() {
|
||||
// Create and print feature-string.
|
||||
char buf[(num_features+1) * 16]; // Max 16 chars per feature.
|
||||
jio_snprintf(buf, sizeof(buf),
|
||||
"ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
|
||||
"ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
|
||||
(has_fsqrt() ? " fsqrt" : ""),
|
||||
(has_isel() ? " isel" : ""),
|
||||
(has_lxarxeh() ? " lxarxeh" : ""),
|
||||
@ -126,7 +126,9 @@ void VM_Version::initialize() {
|
||||
(has_vpmsumb() ? " vpmsumb" : ""),
|
||||
(has_tcheck() ? " tcheck" : ""),
|
||||
(has_mfdscr() ? " mfdscr" : ""),
|
||||
(has_vsx() ? " vsx" : "")
|
||||
(has_vsx() ? " vsx" : ""),
|
||||
(has_ldbrx() ? " ldbrx" : ""),
|
||||
(has_stdbrx() ? " stdbrx" : "")
|
||||
// Make sure number of %s matches num_features!
|
||||
);
|
||||
_features_string = os::strdup(buf);
|
||||
@ -663,6 +665,8 @@ void VM_Version::determine_features() {
|
||||
a->tcheck(0); // code[12] -> tcheck
|
||||
a->mfdscr(R0); // code[13] -> mfdscr
|
||||
a->lxvd2x(VSR0, R3_ARG1); // code[14] -> vsx
|
||||
a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> ldbrx
|
||||
a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[16] -> stdbrx
|
||||
a->blr();
|
||||
|
||||
// Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
|
||||
@ -712,6 +716,8 @@ void VM_Version::determine_features() {
|
||||
if (code[feature_cntr++]) features |= tcheck_m;
|
||||
if (code[feature_cntr++]) features |= mfdscr_m;
|
||||
if (code[feature_cntr++]) features |= vsx_m;
|
||||
if (code[feature_cntr++]) features |= ldbrx_m;
|
||||
if (code[feature_cntr++]) features |= stdbrx_m;
|
||||
|
||||
// Print the detection code.
|
||||
if (PrintAssembly) {
|
||||
|
||||
@ -47,6 +47,8 @@ protected:
|
||||
tcheck,
|
||||
mfdscr,
|
||||
vsx,
|
||||
ldbrx,
|
||||
stdbrx,
|
||||
num_features // last entry to count features
|
||||
};
|
||||
enum Feature_Flag_Set {
|
||||
@ -66,6 +68,8 @@ protected:
|
||||
tcheck_m = (1 << tcheck ),
|
||||
mfdscr_m = (1 << mfdscr ),
|
||||
vsx_m = (1 << vsx ),
|
||||
ldbrx_m = (1 << ldbrx ),
|
||||
stdbrx_m = (1 << stdbrx ),
|
||||
all_features_m = (unsigned long)-1
|
||||
};
|
||||
|
||||
@ -100,6 +104,8 @@ public:
|
||||
static bool has_tcheck() { return (_features & tcheck_m) != 0; }
|
||||
static bool has_mfdscr() { return (_features & mfdscr_m) != 0; }
|
||||
static bool has_vsx() { return (_features & vsx_m) != 0; }
|
||||
static bool has_ldbrx() { return (_features & ldbrx_m) != 0; }
|
||||
static bool has_stdbrx() { return (_features & stdbrx_m) != 0; }
|
||||
|
||||
// Assembler testing
|
||||
static void allow_all();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user