8290082: [PPC64] ZGC C2 load barrier stub needs to preserve vector registers
Reviewed-by: eosterlund, rrich
This commit is contained in:
Martin Doerr
parent
e5491a2605
commit
393dc7ade7
src/hotspot/cpu/ppc
@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2021, 2022, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2021 SAP SE. All rights reserved.
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* Copyright (c) 2021, 2022 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -400,36 +400,40 @@ OptoReg::Name ZBarrierSetAssembler::refine_register(const Node* node, OptoReg::N
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#define __ _masm->
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class ZSaveLiveRegisters {
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private:
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MacroAssembler* _masm;
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RegMask _reg_mask;
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Register _result_reg;
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int _frame_size;
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public:
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ZSaveLiveRegisters(MacroAssembler *masm, ZLoadBarrierStubC2 *stub)
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: _masm(masm), _reg_mask(stub->live()), _result_reg(stub->ref()) {
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const int total_regs_amount = iterate_over_register_mask(ACTION_SAVE);
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const int register_save_size = iterate_over_register_mask(ACTION_COUNT_ONLY) * BytesPerWord;
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_frame_size = align_up(register_save_size, frame::alignment_in_bytes)
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+ frame::abi_reg_args_size;
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__ save_LR_CR(R0);
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__ push_frame_reg_args(total_regs_amount * BytesPerWord, R0);
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__ push_frame(_frame_size, R0);
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iterate_over_register_mask(ACTION_SAVE, _frame_size);
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}
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~ZSaveLiveRegisters() {
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__ pop_frame();
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__ restore_LR_CR(R0);
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iterate_over_register_mask(ACTION_RESTORE, _frame_size);
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iterate_over_register_mask(ACTION_RESTORE);
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__ addi(R1_SP, R1_SP, _frame_size);
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__ restore_LR_CR(R0);
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}
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private:
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enum IterationAction : int {
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ACTION_SAVE = 0,
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ACTION_RESTORE = 1
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ACTION_SAVE,
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ACTION_RESTORE,
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ACTION_COUNT_ONLY
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};
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int iterate_over_register_mask(IterationAction action) {
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int iterate_over_register_mask(IterationAction action, int offset = 0) {
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int reg_save_index = 0;
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RegMaskIterator live_regs_iterator(_reg_mask);
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@ -454,11 +458,11 @@ class ZSaveLiveRegisters {
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reg_save_index++;
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if (action == ACTION_SAVE) {
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_masm->std(std_reg, (intptr_t) -reg_save_index * BytesPerWord, R1_SP);
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_masm->std(std_reg, offset - reg_save_index * BytesPerWord, R1_SP);
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} else if (action == ACTION_RESTORE) {
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_masm->ld(std_reg, (intptr_t) -reg_save_index * BytesPerWord, R1_SP);
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_masm->ld(std_reg, offset - reg_save_index * BytesPerWord, R1_SP);
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} else {
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fatal("Sanity");
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assert(action == ACTION_COUNT_ONLY, "Sanity");
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}
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}
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} else if (vm_reg->is_FloatRegister()) {
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@ -467,19 +471,34 @@ class ZSaveLiveRegisters {
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reg_save_index++;
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if (action == ACTION_SAVE) {
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_masm->stfd(fp_reg, (intptr_t) -reg_save_index * BytesPerWord, R1_SP);
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_masm->stfd(fp_reg, offset - reg_save_index * BytesPerWord, R1_SP);
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} else if (action == ACTION_RESTORE) {
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_masm->lfd(fp_reg, (intptr_t) -reg_save_index * BytesPerWord, R1_SP);
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_masm->lfd(fp_reg, offset - reg_save_index * BytesPerWord, R1_SP);
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} else {
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fatal("Sanity");
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assert(action == ACTION_COUNT_ONLY, "Sanity");
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}
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}
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} else if (vm_reg->is_ConditionRegister()) {
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// NOP. Conditions registers are covered by save_LR_CR
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} else if (vm_reg->is_VectorSRegister()) {
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assert(SuperwordUseVSX, "or should not reach here");
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VectorSRegister vs_reg = vm_reg->as_VectorSRegister();
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if (vs_reg->encoding() >= VSR32->encoding() && vs_reg->encoding() <= VSR51->encoding()) {
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reg_save_index += 2;
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Register spill_addr = R0;
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if (action == ACTION_SAVE) {
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_masm->addi(spill_addr, R1_SP, offset - reg_save_index * BytesPerWord);
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_masm->stxvd2x(vs_reg, spill_addr);
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} else if (action == ACTION_RESTORE) {
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_masm->addi(spill_addr, R1_SP, offset - reg_save_index * BytesPerWord);
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_masm->lxvd2x(vs_reg, spill_addr);
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} else {
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assert(action == ACTION_COUNT_ONLY, "Sanity");
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}
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}
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} else {
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if (vm_reg->is_VectorRegister()) {
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fatal("Vector registers are unsupported. Found register %s", vm_reg->name());
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} else if (vm_reg->is_SpecialRegister()) {
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if (vm_reg->is_SpecialRegister()) {
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fatal("Special registers are unsupported. Found register %s", vm_reg->name());
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} else {
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fatal("Register type is not known");
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@ -495,7 +514,6 @@ class ZSaveLiveRegisters {
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#define __ _masm->
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class ZSetupArguments {
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private:
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MacroAssembler* const _masm;
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const Register _ref;
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const Address _ref_addr;
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@ -257,6 +257,7 @@ register %{
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// ----------------------------
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// Vector-Scalar Registers
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// ----------------------------
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// 1st 32 VSRs are aliases for the FPRs which are already defined above.
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reg_def VSR0 ( SOC, SOC, Op_VecX, 0, VMRegImpl::Bad());
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reg_def VSR1 ( SOC, SOC, Op_VecX, 1, VMRegImpl::Bad());
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reg_def VSR2 ( SOC, SOC, Op_VecX, 2, VMRegImpl::Bad());
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@ -271,56 +272,57 @@ register %{
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reg_def VSR11 ( SOC, SOC, Op_VecX, 11, VMRegImpl::Bad());
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reg_def VSR12 ( SOC, SOC, Op_VecX, 12, VMRegImpl::Bad());
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reg_def VSR13 ( SOC, SOC, Op_VecX, 13, VMRegImpl::Bad());
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reg_def VSR14 ( SOC, SOC, Op_VecX, 14, VMRegImpl::Bad());
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reg_def VSR15 ( SOC, SOC, Op_VecX, 15, VMRegImpl::Bad());
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reg_def VSR16 ( SOC, SOC, Op_VecX, 16, VMRegImpl::Bad());
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reg_def VSR17 ( SOC, SOC, Op_VecX, 17, VMRegImpl::Bad());
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reg_def VSR18 ( SOC, SOC, Op_VecX, 18, VMRegImpl::Bad());
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reg_def VSR19 ( SOC, SOC, Op_VecX, 19, VMRegImpl::Bad());
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reg_def VSR20 ( SOC, SOC, Op_VecX, 20, VMRegImpl::Bad());
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reg_def VSR21 ( SOC, SOC, Op_VecX, 21, VMRegImpl::Bad());
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reg_def VSR22 ( SOC, SOC, Op_VecX, 22, VMRegImpl::Bad());
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reg_def VSR23 ( SOC, SOC, Op_VecX, 23, VMRegImpl::Bad());
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reg_def VSR24 ( SOC, SOC, Op_VecX, 24, VMRegImpl::Bad());
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reg_def VSR25 ( SOC, SOC, Op_VecX, 25, VMRegImpl::Bad());
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reg_def VSR26 ( SOC, SOC, Op_VecX, 26, VMRegImpl::Bad());
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reg_def VSR27 ( SOC, SOC, Op_VecX, 27, VMRegImpl::Bad());
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reg_def VSR28 ( SOC, SOC, Op_VecX, 28, VMRegImpl::Bad());
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reg_def VSR29 ( SOC, SOC, Op_VecX, 29, VMRegImpl::Bad());
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reg_def VSR30 ( SOC, SOC, Op_VecX, 30, VMRegImpl::Bad());
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reg_def VSR31 ( SOC, SOC, Op_VecX, 31, VMRegImpl::Bad());
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reg_def VSR32 ( SOC, SOC, Op_VecX, 32, VMRegImpl::Bad());
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reg_def VSR33 ( SOC, SOC, Op_VecX, 33, VMRegImpl::Bad());
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reg_def VSR34 ( SOC, SOC, Op_VecX, 34, VMRegImpl::Bad());
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reg_def VSR35 ( SOC, SOC, Op_VecX, 35, VMRegImpl::Bad());
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reg_def VSR36 ( SOC, SOC, Op_VecX, 36, VMRegImpl::Bad());
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reg_def VSR37 ( SOC, SOC, Op_VecX, 37, VMRegImpl::Bad());
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reg_def VSR38 ( SOC, SOC, Op_VecX, 38, VMRegImpl::Bad());
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reg_def VSR39 ( SOC, SOC, Op_VecX, 39, VMRegImpl::Bad());
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reg_def VSR40 ( SOC, SOC, Op_VecX, 40, VMRegImpl::Bad());
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reg_def VSR41 ( SOC, SOC, Op_VecX, 41, VMRegImpl::Bad());
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reg_def VSR42 ( SOC, SOC, Op_VecX, 42, VMRegImpl::Bad());
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reg_def VSR43 ( SOC, SOC, Op_VecX, 43, VMRegImpl::Bad());
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reg_def VSR44 ( SOC, SOC, Op_VecX, 44, VMRegImpl::Bad());
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reg_def VSR45 ( SOC, SOC, Op_VecX, 45, VMRegImpl::Bad());
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reg_def VSR46 ( SOC, SOC, Op_VecX, 46, VMRegImpl::Bad());
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reg_def VSR47 ( SOC, SOC, Op_VecX, 47, VMRegImpl::Bad());
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reg_def VSR48 ( SOC, SOC, Op_VecX, 48, VMRegImpl::Bad());
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reg_def VSR49 ( SOC, SOC, Op_VecX, 49, VMRegImpl::Bad());
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reg_def VSR50 ( SOC, SOC, Op_VecX, 50, VMRegImpl::Bad());
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reg_def VSR51 ( SOC, SOC, Op_VecX, 51, VMRegImpl::Bad());
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reg_def VSR52 ( SOC, SOC, Op_VecX, 52, VMRegImpl::Bad());
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reg_def VSR53 ( SOC, SOC, Op_VecX, 53, VMRegImpl::Bad());
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reg_def VSR54 ( SOC, SOC, Op_VecX, 54, VMRegImpl::Bad());
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reg_def VSR55 ( SOC, SOC, Op_VecX, 55, VMRegImpl::Bad());
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reg_def VSR56 ( SOC, SOC, Op_VecX, 56, VMRegImpl::Bad());
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reg_def VSR57 ( SOC, SOC, Op_VecX, 57, VMRegImpl::Bad());
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reg_def VSR58 ( SOC, SOC, Op_VecX, 58, VMRegImpl::Bad());
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reg_def VSR59 ( SOC, SOC, Op_VecX, 59, VMRegImpl::Bad());
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reg_def VSR60 ( SOC, SOC, Op_VecX, 60, VMRegImpl::Bad());
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reg_def VSR61 ( SOC, SOC, Op_VecX, 61, VMRegImpl::Bad());
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reg_def VSR62 ( SOC, SOC, Op_VecX, 62, VMRegImpl::Bad());
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reg_def VSR63 ( SOC, SOC, Op_VecX, 63, VMRegImpl::Bad());
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reg_def VSR14 ( SOC, SOE, Op_VecX, 14, VMRegImpl::Bad());
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reg_def VSR15 ( SOC, SOE, Op_VecX, 15, VMRegImpl::Bad());
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reg_def VSR16 ( SOC, SOE, Op_VecX, 16, VMRegImpl::Bad());
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reg_def VSR17 ( SOC, SOE, Op_VecX, 17, VMRegImpl::Bad());
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reg_def VSR18 ( SOC, SOE, Op_VecX, 18, VMRegImpl::Bad());
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reg_def VSR19 ( SOC, SOE, Op_VecX, 19, VMRegImpl::Bad());
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reg_def VSR20 ( SOC, SOE, Op_VecX, 20, VMRegImpl::Bad());
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reg_def VSR21 ( SOC, SOE, Op_VecX, 21, VMRegImpl::Bad());
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reg_def VSR22 ( SOC, SOE, Op_VecX, 22, VMRegImpl::Bad());
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reg_def VSR23 ( SOC, SOE, Op_VecX, 23, VMRegImpl::Bad());
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reg_def VSR24 ( SOC, SOE, Op_VecX, 24, VMRegImpl::Bad());
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reg_def VSR25 ( SOC, SOE, Op_VecX, 25, VMRegImpl::Bad());
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reg_def VSR26 ( SOC, SOE, Op_VecX, 26, VMRegImpl::Bad());
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reg_def VSR27 ( SOC, SOE, Op_VecX, 27, VMRegImpl::Bad());
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reg_def VSR28 ( SOC, SOE, Op_VecX, 28, VMRegImpl::Bad());
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reg_def VSR29 ( SOC, SOE, Op_VecX, 29, VMRegImpl::Bad());
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reg_def VSR30 ( SOC, SOE, Op_VecX, 30, VMRegImpl::Bad());
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reg_def VSR31 ( SOC, SOE, Op_VecX, 31, VMRegImpl::Bad());
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// 2nd 32 VSRs are aliases for the VRs which are only defined here.
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reg_def VSR32 ( SOC, SOC, Op_VecX, 32, VSR32->as_VMReg());
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reg_def VSR33 ( SOC, SOC, Op_VecX, 33, VSR33->as_VMReg());
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reg_def VSR34 ( SOC, SOC, Op_VecX, 34, VSR34->as_VMReg());
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reg_def VSR35 ( SOC, SOC, Op_VecX, 35, VSR35->as_VMReg());
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reg_def VSR36 ( SOC, SOC, Op_VecX, 36, VSR36->as_VMReg());
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reg_def VSR37 ( SOC, SOC, Op_VecX, 37, VSR37->as_VMReg());
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reg_def VSR38 ( SOC, SOC, Op_VecX, 38, VSR38->as_VMReg());
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reg_def VSR39 ( SOC, SOC, Op_VecX, 39, VSR39->as_VMReg());
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reg_def VSR40 ( SOC, SOC, Op_VecX, 40, VSR40->as_VMReg());
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reg_def VSR41 ( SOC, SOC, Op_VecX, 41, VSR41->as_VMReg());
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reg_def VSR42 ( SOC, SOC, Op_VecX, 42, VSR42->as_VMReg());
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reg_def VSR43 ( SOC, SOC, Op_VecX, 43, VSR43->as_VMReg());
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reg_def VSR44 ( SOC, SOC, Op_VecX, 44, VSR44->as_VMReg());
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reg_def VSR45 ( SOC, SOC, Op_VecX, 45, VSR45->as_VMReg());
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reg_def VSR46 ( SOC, SOC, Op_VecX, 46, VSR46->as_VMReg());
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reg_def VSR47 ( SOC, SOC, Op_VecX, 47, VSR47->as_VMReg());
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reg_def VSR48 ( SOC, SOC, Op_VecX, 48, VSR48->as_VMReg());
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reg_def VSR49 ( SOC, SOC, Op_VecX, 49, VSR49->as_VMReg());
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reg_def VSR50 ( SOC, SOC, Op_VecX, 50, VSR50->as_VMReg());
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reg_def VSR51 ( SOC, SOC, Op_VecX, 51, VSR51->as_VMReg());
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reg_def VSR52 ( SOC, SOE, Op_VecX, 52, VSR52->as_VMReg());
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reg_def VSR53 ( SOC, SOE, Op_VecX, 53, VSR53->as_VMReg());
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reg_def VSR54 ( SOC, SOE, Op_VecX, 54, VSR54->as_VMReg());
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reg_def VSR55 ( SOC, SOE, Op_VecX, 55, VSR55->as_VMReg());
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reg_def VSR56 ( SOC, SOE, Op_VecX, 56, VSR56->as_VMReg());
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reg_def VSR57 ( SOC, SOE, Op_VecX, 57, VSR57->as_VMReg());
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reg_def VSR58 ( SOC, SOE, Op_VecX, 58, VSR58->as_VMReg());
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reg_def VSR59 ( SOC, SOE, Op_VecX, 59, VSR59->as_VMReg());
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reg_def VSR60 ( SOC, SOE, Op_VecX, 60, VSR60->as_VMReg());
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reg_def VSR61 ( SOC, SOE, Op_VecX, 61, VSR61->as_VMReg());
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reg_def VSR62 ( SOC, SOE, Op_VecX, 62, VSR62->as_VMReg());
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reg_def VSR63 ( SOC, SOE, Op_VecX, 63, VSR63->as_VMReg());
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// ----------------------------
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// Specify priority of register selection within phases of register
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2018 SAP SE. All rights reserved.
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* Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2022 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -69,7 +69,11 @@ typedef VMRegImpl* VMReg;
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// v14-v19 Volatile scratch registers
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// v20-v31 Non-volatile registers
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// vrsave Non-volatile 32-bit register
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//
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// ----------------------------------------------
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// On processors with VSX feature:
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// vs0-31 Alias for f0-f31 (64 bit, see above)
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// vs32-63 Alias for v0-31 (128 bit, see above)
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// Use Register as shortcut
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class RegisterImpl;
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2002, 2022, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2020 SAP SE. All rights reserved.
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* Copyright (c) 2012, 2022 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -44,7 +44,13 @@ void VMRegImpl::set_regName() {
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if (reg->encoding() < FloatRegisterImpl::number_of_registers-1)
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freg = freg->successor();
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}
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for ( ; i < ConcreteRegisterImpl::number_of_registers; i++) {
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regName[i] = "NON-GPR-FPR";
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VectorSRegister vsreg = ::as_VectorSRegister(0);
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for ( ; i < ConcreteRegisterImpl::max_vsr; ) {
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regName[i++] = vsreg->name();
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}
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for ( ; i < ConcreteRegisterImpl::number_of_registers; ) {
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regName[i++] = "NON-GPR-FPR-VSR";
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}
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}
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2001, 2021, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
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* Copyright (c) 2001, 2022, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2022 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -35,7 +35,7 @@ inline bool is_FloatRegister() {
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value() < ConcreteRegisterImpl::max_fpr;
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}
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inline bool is_VectorRegister() {
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inline bool is_VectorSRegister() {
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return value() >= ConcreteRegisterImpl::max_fpr &&
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value() < ConcreteRegisterImpl::max_vsr;
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}
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@ -60,6 +60,11 @@ inline FloatRegister as_FloatRegister() {
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return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1);
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}
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inline VectorSRegister as_VectorSRegister() {
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assert(is_VectorSRegister(), "must be");
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return ::as_VectorSRegister(value() - ConcreteRegisterImpl::max_fpr);
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}
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inline bool is_concrete() {
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assert(is_reg(), "must be");
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return is_even(value());
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