From 39f4e4d3c3450ed8fe314e2abde6a6cecd5fa0a5 Mon Sep 17 00:00:00 2001 From: Feilong Jiang Date: Thu, 11 May 2023 01:32:29 +0000 Subject: [PATCH] 8307758: RISC-V: Improve bit test code introduced by JDK-8291555 Co-authored-by: Fei Yang Reviewed-by: fyang --- src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp | 2 +- src/hotspot/cpu/riscv/interp_masm_riscv.cpp | 2 +- src/hotspot/cpu/riscv/riscv.ad | 2 +- src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp index 69b6f200f4b..e65a7b72c49 100644 --- a/src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp +++ b/src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp @@ -135,7 +135,7 @@ void C1_MacroAssembler::unlock_object(Register hdr, Register obj, Register disp_ if (LockingMode == LM_LIGHTWEIGHT) { ld(hdr, Address(obj, oopDesc::mark_offset_in_bytes())); - andi(t0, hdr, markWord::monitor_value); + test_bit(t0, hdr, exact_log2(markWord::monitor_value)); bnez(t0, slow_case, /* is_far */ true); fast_unlock(obj, hdr, t0, t1, slow_case); } else if (LockingMode == LM_LEGACY) { diff --git a/src/hotspot/cpu/riscv/interp_masm_riscv.cpp b/src/hotspot/cpu/riscv/interp_masm_riscv.cpp index 093a762cc06..dffb3738048 100644 --- a/src/hotspot/cpu/riscv/interp_masm_riscv.cpp +++ b/src/hotspot/cpu/riscv/interp_masm_riscv.cpp @@ -922,7 +922,7 @@ void InterpreterMacroAssembler::unlock_object(Register lock_reg) bne(tmp1, obj_reg, slow_case); ld(header_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); - andi(t0, header_reg, markWord::monitor_value); + test_bit(t0, header_reg, exact_log2(markWord::monitor_value)); bnez(t0, slow_case); fast_unlock(obj_reg, header_reg, swap_reg, t0, slow_case); j(count); diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad index a890313a3a9..9e352e086ba 100644 --- a/src/hotspot/cpu/riscv/riscv.ad +++ b/src/hotspot/cpu/riscv/riscv.ad @@ -2663,7 +2663,7 @@ encode %{ // If the owner is anonymous, we need to fix it -- in an outline stub. Register tmp2 = disp_hdr; __ ld(tmp2, Address(tmp, ObjectMonitor::owner_offset_in_bytes())); - __ andi(t0, tmp2, (int64_t)ObjectMonitor::ANONYMOUS_OWNER); + __ test_bit(t0, tmp2, exact_log2(ObjectMonitor::ANONYMOUS_OWNER)); C2HandleAnonOMOwnerStub* stub = new (Compile::current()->comp_arena()) C2HandleAnonOMOwnerStub(tmp, tmp2); Compile::current()->output()->add_stub(stub); __ bnez(t0, stub->entry(), /* is_far */ true); diff --git a/src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp b/src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp index 643550f80a6..70fcde9445c 100644 --- a/src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp +++ b/src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp @@ -1828,7 +1828,7 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, } else { assert(LockingMode == LM_LIGHTWEIGHT, ""); __ ld(old_hdr, Address(obj_reg, oopDesc::mark_offset_in_bytes())); - __ andi(t0, old_hdr, markWord::monitor_value); + __ test_bit(t0, old_hdr, exact_log2(markWord::monitor_value)); __ bnez(t0, slow_path_unlock); __ fast_unlock(obj_reg, old_hdr, swap_reg, t0, slow_path_unlock); __ decrement(Address(xthread, JavaThread::held_monitor_count_offset()));