diff --git a/src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp b/src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp
index 61c8036b1ce..3a8f1ab839d 100644
--- a/src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp
+++ b/src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp
@@ -963,22 +963,33 @@ void C2_MacroAssembler::vpuminmax(int opcode, BasicType elem_bt, XMMRegister dst
 }
 
 void C2_MacroAssembler::vpuminmaxq(int opcode, XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister xtmp1, XMMRegister xtmp2, int vlen_enc) {
-  // T1 = -1
-  vpcmpeqq(xtmp1, xtmp1, xtmp1, vlen_enc);
-  // T1 = -1 << 63
-  vpsllq(xtmp1, xtmp1, 63, vlen_enc);
-  // Convert SRC2 to signed value i.e. T2 = T1 + SRC2
-  vpaddq(xtmp2, xtmp1, src2, vlen_enc);
-  // Convert SRC1 to signed value i.e. T1 = T1 + SRC1
-  vpaddq(xtmp1, xtmp1, src1, vlen_enc);
-  // Mask = T2 > T1
-  vpcmpgtq(xtmp1, xtmp2, xtmp1, vlen_enc);
-  if (opcode == Op_UMaxV) {
-    // Res = Mask ? Src2 : Src1
-    vpblendvb(dst, src1, src2, xtmp1, vlen_enc);
+  // For optimality, leverage a full vector width of 512 bits
+  // for operations over smaller vector sizes on AVX512 targets.
+  if (VM_Version::supports_evex() && !VM_Version::supports_avx512vl()) {
+    if (opcode == Op_UMaxV) {
+      evpmaxuq(dst, k0, src1, src2, false, Assembler::AVX_512bit);
+    } else {
+      assert(opcode == Op_UMinV, "required");
+      evpminuq(dst, k0, src1, src2, false, Assembler::AVX_512bit);
+    }
   } else {
-    // Res = Mask ? Src1 : Src2
-    vpblendvb(dst, src2, src1, xtmp1, vlen_enc);
+    // T1 = -1
+    vpcmpeqq(xtmp1, xtmp1, xtmp1, vlen_enc);
+    // T1 = -1 << 63
+    vpsllq(xtmp1, xtmp1, 63, vlen_enc);
+    // Convert SRC2 to signed value i.e. T2 = T1 + SRC2
+    vpaddq(xtmp2, xtmp1, src2, vlen_enc);
+    // Convert SRC1 to signed value i.e. T1 = T1 + SRC1
+    vpaddq(xtmp1, xtmp1, src1, vlen_enc);
+    // Mask = T2 > T1
+    vpcmpgtq(xtmp1, xtmp2, xtmp1, vlen_enc);
+    if (opcode == Op_UMaxV) {
+      // Res = Mask ? Src2 : Src1
+      vpblendvb(dst, src1, src2, xtmp1, vlen_enc);
+    } else {
+      // Res = Mask ? Src1 : Src2
+      vpblendvb(dst, src2, src1, xtmp1, vlen_enc);
+    }
   }
 }
 
diff --git a/src/hotspot/cpu/x86/x86.ad b/src/hotspot/cpu/x86/x86.ad
index e5222d38632..f980643396f 100644
--- a/src/hotspot/cpu/x86/x86.ad
+++ b/src/hotspot/cpu/x86/x86.ad
@@ -2138,10 +2138,13 @@ bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType
     case Op_StoreVectorScatterMasked:
       return true;
 
-    case Op_MaxV:
-    case Op_MinV:
     case Op_UMinV:
     case Op_UMaxV:
+      if (size_in_bits < 512 && !VM_Version::supports_avx512vl()) {
+        return false;
+      } // fallthrough
+    case Op_MaxV:
+    case Op_MinV:
       if (is_subword_type(bt) && !VM_Version::supports_avx512bw()) {
         return false; // Implementation limitation
       }