From 40f3d50badc20db5fbfcd485447e634778d03248 Mon Sep 17 00:00:00 2001 From: SendaoYan Date: Tue, 29 Oct 2024 23:17:52 +0000 Subject: [PATCH] 8343211: Compile error: redefinition of 'Assembler::evmovdquw(XMMRegister,KRegister,XMMRegister,bool,int)' Reviewed-by: vpaprotski, sviswanathan, thartmann, shade --- src/hotspot/cpu/x86/assembler_x86.cpp | 12 ------------ .../sha/predicate/IntrinsicPredicates.java | 2 +- 2 files changed, 1 insertion(+), 13 deletions(-) diff --git a/src/hotspot/cpu/x86/assembler_x86.cpp b/src/hotspot/cpu/x86/assembler_x86.cpp index 1155166d0da..e4ab99bf1c3 100644 --- a/src/hotspot/cpu/x86/assembler_x86.cpp +++ b/src/hotspot/cpu/x86/assembler_x86.cpp @@ -3590,18 +3590,6 @@ void Assembler::evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) { evmovdquw(dst, k0, src, /*merge*/ false, vector_len); } -void Assembler::evmovdquw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { - assert(vector_len <= AVX_256bit ? VM_Version::supports_avx512vlbw() : VM_Version::supports_avx512bw(), ""); - InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); - attributes.set_embedded_opmask_register_specifier(mask); - attributes.set_is_evex_instruction(); - if (merge) { - attributes.reset_is_clear_context(); - } - int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); - emit_int16(0x6F, (0xC0 | encode)); -} - void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) { // Unmasked instruction evmovdquw(dst, k0, src, /*merge*/ false, vector_len); diff --git a/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java b/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java index 19257f81614..0c53c36af1d 100644 --- a/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java +++ b/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, 2022, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2024, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it