7029017: Additional architecture support for c2 compiler
Enables cross building of a c2 VM. Support masking of shift counts when the processor architecture mandates it. Reviewed-by: kvn, never
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@ -102,7 +102,7 @@ all: $(EXEC)
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$(EXEC) : $(OBJECTS)
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$(EXEC) : $(OBJECTS)
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@echo Making adlc
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@echo Making adlc
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$(QUIETLY) $(LINK_NOPROF.CC) -o $(EXEC) $(OBJECTS)
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$(QUIETLY) $(HOST.LINK_NOPROF.CC) -o $(EXEC) $(OBJECTS)
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# Random dependencies:
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# Random dependencies:
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$(OBJECTS): opcodes.hpp classes.hpp adlc.hpp adlcVMDeps.hpp adlparse.hpp archDesc.hpp arena.hpp dict2.hpp filebuff.hpp forms.hpp formsopt.hpp formssel.hpp
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$(OBJECTS): opcodes.hpp classes.hpp adlc.hpp adlcVMDeps.hpp adlparse.hpp archDesc.hpp arena.hpp dict2.hpp filebuff.hpp forms.hpp formsopt.hpp formssel.hpp
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@ -204,14 +204,14 @@ PROCESS_AD_FILES = awk '{ \
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$(OUTDIR)/%.o: %.cpp
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$(OUTDIR)/%.o: %.cpp
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@echo Compiling $<
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@echo Compiling $<
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$(QUIETLY) $(REMOVE_TARGET)
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$(QUIETLY) $(REMOVE_TARGET)
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$(QUIETLY) $(COMPILE.CC) -o $@ $< $(COMPILE_DONE)
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$(QUIETLY) $(HOST.COMPILE.CC) -o $@ $< $(COMPILE_DONE)
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# Some object files are given a prefix, to disambiguate
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# Some object files are given a prefix, to disambiguate
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# them from objects of the same name built for the VM.
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# them from objects of the same name built for the VM.
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$(OUTDIR)/adlc-%.o: %.cpp
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$(OUTDIR)/adlc-%.o: %.cpp
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@echo Compiling $<
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@echo Compiling $<
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$(QUIETLY) $(REMOVE_TARGET)
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$(QUIETLY) $(REMOVE_TARGET)
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$(QUIETLY) $(COMPILE.CC) -o $@ $< $(COMPILE_DONE)
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$(QUIETLY) $(HOST.COMPILE.CC) -o $@ $< $(COMPILE_DONE)
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# #########################################################################
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# #########################################################################
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@ -30,9 +30,13 @@
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ifdef CROSS_COMPILE_ARCH
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ifdef CROSS_COMPILE_ARCH
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CPP = $(ALT_COMPILER_PATH)/g++
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CPP = $(ALT_COMPILER_PATH)/g++
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CC = $(ALT_COMPILER_PATH)/gcc
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CC = $(ALT_COMPILER_PATH)/gcc
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HOSTCPP = g++
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HOSTCC = gcc
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else
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else
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CPP = g++
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CPP = g++
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CC = gcc
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CC = gcc
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HOSTCPP = $(CPP)
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HOSTCC = $(CC)
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endif
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endif
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AS = $(CC) -c
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AS = $(CC) -c
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@ -55,6 +55,14 @@ LINK_NOPROF.CC = $(CCC) $(LFLAGS) $(AOUT_FLAGS)
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LINK_LIB.CC = $(CCC) $(LFLAGS) $(SHARED_FLAG)
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LINK_LIB.CC = $(CCC) $(LFLAGS) $(SHARED_FLAG)
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PREPROCESS.CC = $(CC_COMPILE) -E
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PREPROCESS.CC = $(CC_COMPILE) -E
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# cross compiling the jvm with c2 requires host compilers to build
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# adlc tool
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HOST.CC_COMPILE = $(HOSTCPP) $(CPPFLAGS) $(CFLAGS)
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HOST.COMPILE.CC = $(HOST.CC_COMPILE) -c
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HOST.LINK_NOPROF.CC = $(HOSTCPP) $(LFLAGS) $(AOUT_FLAGS)
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# Effect of REMOVE_TARGET is to delete out-of-date files during "gnumake -k".
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# Effect of REMOVE_TARGET is to delete out-of-date files during "gnumake -k".
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REMOVE_TARGET = rm -f $@
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REMOVE_TARGET = rm -f $@
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@ -29,6 +29,9 @@ CPP = CC
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CC = cc
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CC = cc
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AS = $(CC) -c
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AS = $(CC) -c
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HOSTCPP = $(CPP)
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HOSTCC = $(CC)
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ARCHFLAG = $(ARCHFLAG/$(BUILDARCH))
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ARCHFLAG = $(ARCHFLAG/$(BUILDARCH))
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ARCHFLAG/i486 = -m32
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ARCHFLAG/i486 = -m32
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ARCHFLAG/amd64 = -m64
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ARCHFLAG/amd64 = -m64
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@ -1843,6 +1843,10 @@ const int Matcher::init_array_short_size = 8 * BytesPerLong;
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// registers? True for Intel but false for most RISCs
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// registers? True for Intel but false for most RISCs
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const bool Matcher::clone_shift_expressions = false;
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const bool Matcher::clone_shift_expressions = false;
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// Do we need to mask the count passed to shift instructions or does
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// the cpu only look at the lower 5/6 bits anyway?
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const bool Matcher::need_masked_shift_count = false;
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bool Matcher::narrow_oop_use_complex_address() {
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bool Matcher::narrow_oop_use_complex_address() {
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NOT_LP64(ShouldNotCallThis());
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NOT_LP64(ShouldNotCallThis());
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assert(UseCompressedOops, "only for compressed oops code");
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assert(UseCompressedOops, "only for compressed oops code");
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@ -1393,6 +1393,10 @@ const int Matcher::init_array_short_size = 8 * BytesPerLong;
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// registers? True for Intel but false for most RISCs
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// registers? True for Intel but false for most RISCs
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const bool Matcher::clone_shift_expressions = true;
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const bool Matcher::clone_shift_expressions = true;
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// Do we need to mask the count passed to shift instructions or does
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// the cpu only look at the lower 5/6 bits anyway?
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const bool Matcher::need_masked_shift_count = false;
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bool Matcher::narrow_oop_use_complex_address() {
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bool Matcher::narrow_oop_use_complex_address() {
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ShouldNotCallThis();
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ShouldNotCallThis();
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return true;
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return true;
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@ -2000,6 +2000,10 @@ const int Matcher::init_array_short_size = 8 * BytesPerLong;
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// into registers? True for Intel but false for most RISCs
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// into registers? True for Intel but false for most RISCs
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const bool Matcher::clone_shift_expressions = true;
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const bool Matcher::clone_shift_expressions = true;
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// Do we need to mask the count passed to shift instructions or does
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// the cpu only look at the lower 5/6 bits anyway?
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const bool Matcher::need_masked_shift_count = false;
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bool Matcher::narrow_oop_use_complex_address() {
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bool Matcher::narrow_oop_use_complex_address() {
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assert(UseCompressedOops, "only for compressed oops code");
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assert(UseCompressedOops, "only for compressed oops code");
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return (LogMinObjAlignmentInBytes <= 3);
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return (LogMinObjAlignmentInBytes <= 3);
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@ -239,6 +239,11 @@ int main(int argc, char *argv[])
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AD.addInclude(AD._CPP_file, "assembler_sparc.inline.hpp");
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AD.addInclude(AD._CPP_file, "assembler_sparc.inline.hpp");
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AD.addInclude(AD._CPP_file, "nativeInst_sparc.hpp");
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AD.addInclude(AD._CPP_file, "nativeInst_sparc.hpp");
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AD.addInclude(AD._CPP_file, "vmreg_sparc.inline.hpp");
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AD.addInclude(AD._CPP_file, "vmreg_sparc.inline.hpp");
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#endif
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#ifdef TARGET_ARCH_arm
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AD.addInclude(AD._CPP_file, "assembler_arm.inline.hpp");
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AD.addInclude(AD._CPP_file, "nativeInst_arm.hpp");
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AD.addInclude(AD._CPP_file, "vmreg_arm.inline.hpp");
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#endif
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#endif
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AD.addInclude(AD._HPP_file, "memory/allocation.hpp");
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AD.addInclude(AD._HPP_file, "memory/allocation.hpp");
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AD.addInclude(AD._HPP_file, "opto/machnode.hpp");
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AD.addInclude(AD._HPP_file, "opto/machnode.hpp");
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@ -673,7 +673,7 @@ void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
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case Op_RegD:
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case Op_RegD:
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lrg.set_num_regs(2);
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lrg.set_num_regs(2);
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// Define platform specific register pressure
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// Define platform specific register pressure
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#ifdef SPARC
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#if defined(SPARC) || defined(ARM)
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lrg.set_reg_pressure(2);
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lrg.set_reg_pressure(2);
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#elif defined(IA32)
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#elif defined(IA32)
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if( ireg == Op_RegL ) {
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if( ireg == Op_RegL ) {
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@ -2544,6 +2544,36 @@ static void final_graph_reshaping_impl( Node *n, Final_Reshape_Counts &frc ) {
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frc.inc_inner_loop_count();
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frc.inc_inner_loop_count();
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}
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}
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break;
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break;
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case Op_LShiftI:
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case Op_RShiftI:
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case Op_URShiftI:
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case Op_LShiftL:
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case Op_RShiftL:
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case Op_URShiftL:
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if (Matcher::need_masked_shift_count) {
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// The cpu's shift instructions don't restrict the count to the
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// lower 5/6 bits. We need to do the masking ourselves.
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Node* in2 = n->in(2);
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juint mask = (n->bottom_type() == TypeInt::INT) ? (BitsPerInt - 1) : (BitsPerLong - 1);
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const TypeInt* t = in2->find_int_type();
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if (t != NULL && t->is_con()) {
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juint shift = t->get_con();
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if (shift > mask) { // Unsigned cmp
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Compile* C = Compile::current();
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n->set_req(2, ConNode::make(C, TypeInt::make(shift & mask)));
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}
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} else {
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if (t == NULL || t->_lo < 0 || t->_hi > (int)mask) {
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Compile* C = Compile::current();
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Node* shift = new (C, 3) AndINode(in2, ConNode::make(C, TypeInt::make(mask)));
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n->set_req(2, shift);
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}
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}
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if (in2->outcnt() == 0) { // Remove dead node
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in2->disconnect_inputs(NULL);
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}
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}
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break;
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default:
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default:
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assert( !n->is_Call(), "" );
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assert( !n->is_Call(), "" );
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assert( !n->is_Mem(), "" );
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assert( !n->is_Mem(), "" );
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@ -42,6 +42,9 @@
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#ifdef TARGET_ARCH_MODEL_zero
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#ifdef TARGET_ARCH_MODEL_zero
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# include "adfiles/ad_zero.hpp"
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# include "adfiles/ad_zero.hpp"
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#endif
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#endif
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#ifdef TARGET_ARCH_MODEL_arm
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# include "adfiles/ad_arm.hpp"
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#endif
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// Optimization - Graph Style
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// Optimization - Graph Style
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@ -49,6 +49,9 @@
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#ifdef TARGET_ARCH_MODEL_zero
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#ifdef TARGET_ARCH_MODEL_zero
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# include "adfiles/ad_zero.hpp"
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# include "adfiles/ad_zero.hpp"
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#endif
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#endif
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#ifdef TARGET_ARCH_MODEL_arm
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# include "adfiles/ad_arm.hpp"
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#endif
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OptoReg::Name OptoReg::c_frame_pointer;
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OptoReg::Name OptoReg::c_frame_pointer;
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@ -427,6 +427,11 @@ public:
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// Do ints take an entire long register or just half?
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// Do ints take an entire long register or just half?
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static const bool int_in_long;
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static const bool int_in_long;
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// Do the processor's shift instructions only use the low 5/6 bits
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// of the count for 32/64 bit ints? If not we need to do the masking
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// ourselves.
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static const bool need_masked_shift_count;
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// This routine is run whenever a graph fails to match.
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// This routine is run whenever a graph fails to match.
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// If it returns, the compiler should bailout to interpreter without error.
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// If it returns, the compiler should bailout to interpreter without error.
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// In non-product mode, SoftMatchFailure is false to detect non-canonical
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// In non-product mode, SoftMatchFailure is false to detect non-canonical
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