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8268739: AArch64: Build failure after JDK-8267663

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Reviewed-by: aph, dholmes
This commit is contained in:
Eric Liu 2021-06-17 02:47:00 +00:00 committed by Pengfei Li
parent 112ddb7633
commit 4c9aefdb61
4 changed files with 49 additions and 47 deletions
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45
src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -27,6 +27,7 @@
#include "asm/assembler.inline.hpp"
#include "opto/c2_MacroAssembler.hpp"
#include "opto/intrinsicnode.hpp"
#include "opto/subnode.hpp"
#include "runtime/stubRoutines.hpp"
#ifdef PRODUCT
@ -832,3 +833,45 @@ void C2_MacroAssembler::string_compare(Register str1, Register str2,
BLOCK_COMMENT("} string_compare");
}
void C2_MacroAssembler::neon_compare(FloatRegister dst, BasicType bt, FloatRegister src1,
FloatRegister src2, int cond, bool isQ) {
SIMD_Arrangement size = esize2arrangement(type2aelembytes(bt), isQ);
if (bt == T_FLOAT || bt == T_DOUBLE) {
switch (cond) {
case BoolTest::eq: fcmeq(dst, size, src1, src2); break;
case BoolTest::ne: {
fcmeq(dst, size, src1, src2);
notr(dst, T16B, dst);
break;
}
case BoolTest::ge: fcmge(dst, size, src1, src2); break;
case BoolTest::gt: fcmgt(dst, size, src1, src2); break;
case BoolTest::le: fcmge(dst, size, src2, src1); break;
case BoolTest::lt: fcmgt(dst, size, src2, src1); break;
default:
assert(false, "unsupported");
ShouldNotReachHere();
}
} else {
switch (cond) {
case BoolTest::eq: cmeq(dst, size, src1, src2); break;
case BoolTest::ne: {
cmeq(dst, size, src1, src2);
notr(dst, T16B, dst);
break;
}
case BoolTest::ge: cmge(dst, size, src1, src2); break;
case BoolTest::gt: cmgt(dst, size, src1, src2); break;
case BoolTest::le: cmge(dst, size, src2, src1); break;
case BoolTest::lt: cmgt(dst, size, src2, src1); break;
case BoolTest::uge: cmhs(dst, size, src1, src2); break;
case BoolTest::ugt: cmhi(dst, size, src1, src2); break;
case BoolTest::ult: cmhi(dst, size, src2, src1); break;
case BoolTest::ule: cmhs(dst, size, src2, src1); break;
default:
assert(false, "unsupported");
ShouldNotReachHere();
}
}
}

6
src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -49,4 +49,8 @@
Register ch, Register result,
Register tmp1, Register tmp2, Register tmp3);
// SIMD&FP comparison
void neon_compare(FloatRegister dst, BasicType bt, FloatRegister src1,
FloatRegister src2, int cond, bool isQ);
#endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP

43
src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
View File

@ -5339,49 +5339,6 @@ void MacroAssembler::safepoint_isb() {
#endif
}
void MacroAssembler::neon_compare(FloatRegister dst, BasicType bt, FloatRegister src1,
FloatRegister src2, int cond, bool isQ) {
SIMD_Arrangement size = esize2arrangement(type2aelembytes(bt), isQ);
if (bt == T_FLOAT || bt == T_DOUBLE) {
switch (cond) {
case BoolTest::eq: fcmeq(dst, size, src1, src2); break;
case BoolTest::ne: {
fcmeq(dst, size, src1, src2);
notr(dst, T16B, dst);
break;
}
case BoolTest::ge: fcmge(dst, size, src1, src2); break;
case BoolTest::gt: fcmgt(dst, size, src1, src2); break;
case BoolTest::le: fcmge(dst, size, src2, src1); break;
case BoolTest::lt: fcmgt(dst, size, src2, src1); break;
default:
assert(false, "unsupported");
ShouldNotReachHere();
}
} else {
switch (cond) {
case BoolTest::eq: cmeq(dst, size, src1, src2); break;
case BoolTest::ne: {
cmeq(dst, size, src1, src2);
notr(dst, T16B, dst);
break;
}
case BoolTest::ge: cmge(dst, size, src1, src2); break;
case BoolTest::gt: cmgt(dst, size, src1, src2); break;
case BoolTest::le: cmge(dst, size, src2, src1); break;
case BoolTest::lt: cmgt(dst, size, src2, src1); break;
case BoolTest::uge: cmhs(dst, size, src1, src2); break;
case BoolTest::ugt: cmhi(dst, size, src1, src2); break;
case BoolTest::ult: cmhi(dst, size, src2, src1); break;
case BoolTest::ule: cmhs(dst, size, src2, src1); break;
default:
assert(false, "unsupported");
ShouldNotReachHere();
}
}
}
#ifndef PRODUCT
void MacroAssembler::verify_cross_modify_fence_not_required() {
if (VerifyCrossModifyFence) {

2
src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp
View File

@ -1058,8 +1058,6 @@ public:
bool acquire, bool release, bool weak,
Register result);
// SIMD&FP comparison
void neon_compare(FloatRegister dst, BasicType bt, FloatRegister src1, FloatRegister src2, int cond, bool isQ);
private:
void compare_eq(Register rn, Register rm, enum operand_size size);