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8295396: RISC-V: Cleanup useless CompressibleRegions

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Reviewed-by: fyang
This commit is contained in:
Xiaolin Zheng 2022-10-18 01:15:49 +00:00 committed by Fei Yang
parent 692cdab2be
commit 529cc48f35
2 changed files with 0 additions and 68 deletions
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12
src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
View File

@ -1203,8 +1203,6 @@ int MacroAssembler::bitset_to_regs(unsigned int bitset, unsigned char* regs) {
// Return the number of words pushed
int MacroAssembler::push_reg(unsigned int bitset, Register stack) {
DEBUG_ONLY(int words_pushed = 0;)
CompressibleRegion cr(this);
unsigned char regs[32];
int count = bitset_to_regs(bitset, regs);
// reserve one slot to align for odd count
@ -1225,8 +1223,6 @@ int MacroAssembler::push_reg(unsigned int bitset, Register stack) {
int MacroAssembler::pop_reg(unsigned int bitset, Register stack) {
DEBUG_ONLY(int words_popped = 0;)
CompressibleRegion cr(this);
unsigned char regs[32];
int count = bitset_to_regs(bitset, regs);
// reserve one slot to align for odd count
@ -1248,7 +1244,6 @@ int MacroAssembler::pop_reg(unsigned int bitset, Register stack) {
// Push floating-point registers in the bitset supplied.
// Return the number of words pushed
int MacroAssembler::push_fp(unsigned int bitset, Register stack) {
CompressibleRegion cr(this);
DEBUG_ONLY(int words_pushed = 0;)
unsigned char regs[32];
int count = bitset_to_regs(bitset, regs);
@ -1269,7 +1264,6 @@ int MacroAssembler::push_fp(unsigned int bitset, Register stack) {
}
int MacroAssembler::pop_fp(unsigned int bitset, Register stack) {
CompressibleRegion cr(this);
DEBUG_ONLY(int words_popped = 0;)
unsigned char regs[32];
int count = bitset_to_regs(bitset, regs);
@ -1293,7 +1287,6 @@ int MacroAssembler::pop_fp(unsigned int bitset, Register stack) {
// Push vector registers in the bitset supplied.
// Return the number of words pushed
int MacroAssembler::push_v(unsigned int bitset, Register stack) {
CompressibleRegion cr(this);
int vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
// Scan bitset to accumulate register pairs
@ -1309,7 +1302,6 @@ int MacroAssembler::push_v(unsigned int bitset, Register stack) {
}
int MacroAssembler::pop_v(unsigned int bitset, Register stack) {
CompressibleRegion cr(this);
int vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
// Scan bitset to accumulate register pairs
@ -1326,7 +1318,6 @@ int MacroAssembler::pop_v(unsigned int bitset, Register stack) {
#endif // COMPILER2
void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
CompressibleRegion cr(this);
// Push integer registers x7, x10-x17, x28-x31.
push_reg(RegSet::of(x7) + RegSet::range(x10, x17) + RegSet::range(x28, x31) - exclude, sp);
@ -1341,7 +1332,6 @@ void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
}
void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
CompressibleRegion cr(this);
int offset = 0;
for (int i = 0; i < 32; i++) {
if (i <= f7->encoding() || i >= f28->encoding() || (i >= f10->encoding() && i <= f17->encoding())) {
@ -1354,7 +1344,6 @@ void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
}
void MacroAssembler::push_CPU_state(bool save_vectors, int vector_size_in_bytes) {
CompressibleRegion cr(this);
// integer registers, except zr(x0) & ra(x1) & sp(x2) & gp(x3) & tp(x4)
push_reg(RegSet::range(x5, x31), sp);
@ -1376,7 +1365,6 @@ void MacroAssembler::push_CPU_state(bool save_vectors, int vector_size_in_bytes)
}
void MacroAssembler::pop_CPU_state(bool restore_vectors, int vector_size_in_bytes) {
CompressibleRegion cr(this);
// vector registers
if (restore_vectors) {
vsetvli(t0, x0, Assembler::e64, Assembler::m8);

56
src/hotspot/cpu/riscv/riscv.ad
View File

@ -1224,7 +1224,6 @@ void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
C2_MacroAssembler _masm(&cbuf);
Assembler::CompressibleRegion cr(&_masm);
__ ebreak();
}
@ -1532,7 +1531,6 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo
uint ireg = ideal_reg();
if (ireg == Op_VecA && cbuf) {
C2_MacroAssembler _masm(cbuf);
Assembler::CompressibleRegion cr(&_masm);
int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
// stack to stack
@ -1553,7 +1551,6 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo
}
} else if (cbuf != NULL) {
C2_MacroAssembler _masm(cbuf);
Assembler::CompressibleRegion cr(&_masm);
switch (src_lo_rc) {
case rc_int:
if (dst_lo_rc == rc_int) { // gpr --> gpr copy
@ -2108,7 +2105,6 @@ encode %{
enc_class riscv_enc_li_imm(iRegIorL dst, immIorL src) %{
C2_MacroAssembler _masm(&cbuf);
Assembler::CompressibleRegion cr(&_masm);
int64_t con = (int64_t)$src$$constant;
Register dst_reg = as_Register($dst$$reg);
__ mv(dst_reg, con);
@ -2135,7 +2131,6 @@ encode %{
enc_class riscv_enc_mov_p1(iRegP dst) %{
C2_MacroAssembler _masm(&cbuf);
Assembler::CompressibleRegion cr(&_masm);
Register dst_reg = as_Register($dst$$reg);
__ mv(dst_reg, 1);
%}
@ -2557,14 +2552,12 @@ encode %{
enc_class riscv_enc_tail_call(iRegP jump_target) %{
C2_MacroAssembler _masm(&cbuf);
Assembler::CompressibleRegion cr(&_masm);
Register target_reg = as_Register($jump_target$$reg);
__ jr(target_reg);
%}
enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
C2_MacroAssembler _masm(&cbuf);
Assembler::CompressibleRegion cr(&_masm);
Register target_reg = as_Register($jump_target$$reg);
// exception oop should be in x10
// ret addr has been popped into ra
@ -2580,7 +2573,6 @@ encode %{
enc_class riscv_enc_ret() %{
C2_MacroAssembler _masm(&cbuf);
Assembler::CompressibleRegion cr(&_masm);
__ ret();
%}
@ -4565,7 +4557,6 @@ instruct loadI(iRegINoSp dst, memory mem)
format %{ "lw $dst, $mem\t# int, #@loadI" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
%}
@ -4581,7 +4572,6 @@ instruct loadI2L(iRegLNoSp dst, memory mem)
format %{ "lw $dst, $mem\t# int, #@loadI2L" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
%}
@ -4612,7 +4602,6 @@ instruct loadL(iRegLNoSp dst, memory mem)
format %{ "ld $dst, $mem\t# int, #@loadL" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
%}
@ -4644,7 +4633,6 @@ instruct loadP(iRegPNoSp dst, memory mem)
format %{ "ld $dst, $mem\t# ptr, #@loadP" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
%}
@ -4675,7 +4663,6 @@ instruct loadKlass(iRegPNoSp dst, memory mem)
format %{ "ld $dst, $mem\t# class, #@loadKlass" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
%}
@ -4721,7 +4708,6 @@ instruct loadD(fRegD dst, memory mem)
format %{ "fld $dst, $mem\t# double, #@loadD" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
%}
@ -5006,7 +4992,6 @@ instruct storeI(iRegIorL2I src, memory mem)
format %{ "sw $src, $mem\t# int, #@storeI" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
%}
@ -5036,7 +5021,6 @@ instruct storeL(iRegL src, memory mem)
format %{ "sd $src, $mem\t# long, #@storeL" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
%}
@ -5067,7 +5051,6 @@ instruct storeP(iRegP src, memory mem)
format %{ "sd $src, $mem\t# ptr, #@storeP" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
%}
@ -5098,7 +5081,6 @@ instruct storeN(iRegN src, memory mem)
format %{ "sw $src, $mem\t# compressed ptr, #@storeN" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
%}
@ -5143,7 +5125,6 @@ instruct storeD(fRegD src, memory mem)
format %{ "fsd $src, $mem\t# double, #@storeD" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
%}
@ -5159,7 +5140,6 @@ instruct storeNKlass(iRegN src, memory mem)
format %{ "sw $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
%}
@ -6341,7 +6321,6 @@ instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
format %{ "addw $dst, $src1, $src2\t#@addI_reg_reg" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ addw(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg));
@ -6357,7 +6336,6 @@ instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
int32_t con = (int32_t)$src2$$constant;
__ addiw(as_Register($dst$$reg),
as_Register($src1$$reg),
@ -6374,7 +6352,6 @@ instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ addiw(as_Register($dst$$reg),
as_Register($src1$$reg),
$src2$$constant);
@ -6391,7 +6368,6 @@ instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ add(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg));
@ -6407,7 +6383,6 @@ instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
format %{ "slli $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
%}
@ -6423,7 +6398,6 @@ instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
format %{ "addi $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
// src2 is imm, so actually call the addi
__ add(as_Register($dst$$reg),
as_Register($src1$$reg),
@ -6440,7 +6414,6 @@ instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
format %{ "add $dst, $src1, $src2\t#@addL_reg_reg" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ add(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg));
@ -6456,7 +6429,6 @@ instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
format %{ "addi $dst, $src1, $src2\t#@addL_reg_imm" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
// src2 is imm, so actually call the addi
__ add(as_Register($dst$$reg),
as_Register($src1$$reg),
@ -6474,7 +6446,6 @@ instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
format %{ "subw $dst, $src1, $src2\t#@subI_reg_reg" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ subw(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg));
@ -6491,7 +6462,6 @@ instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
format %{ "addiw $dst, $src1, -$src2\t#@subI_reg_imm" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
// src2 is imm, so actually call the addiw
__ subw(as_Register($dst$$reg),
as_Register($src1$$reg),
@ -6508,7 +6478,6 @@ instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
format %{ "sub $dst, $src1, $src2\t#@subL_reg_reg" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ sub(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg));
@ -6524,7 +6493,6 @@ instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
format %{ "addi $dst, $src1, -$src2\t#@subL_reg_imm" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
// src2 is imm, so actually call the addi
__ sub(as_Register($dst$$reg),
as_Register($src1$$reg),
@ -6654,7 +6622,6 @@ instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
%}
ins_pipe(ialu_reg_shift);
@ -6810,7 +6777,6 @@ instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
format %{ "slli $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
// the shift amount is encoded in the lower
// 6 bits of the I-immediate field for RV64I
__ slli(as_Register($dst$$reg),
@ -6846,7 +6812,6 @@ instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
format %{ "srli $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
// the shift amount is encoded in the lower
// 6 bits of the I-immediate field for RV64I
__ srli(as_Register($dst$$reg),
@ -6865,7 +6830,6 @@ instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
format %{ "srli $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
// the shift amount is encoded in the lower
// 6 bits of the I-immediate field for RV64I
__ srli(as_Register($dst$$reg),
@ -6901,7 +6865,6 @@ instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
format %{ "srai $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
// the shift amount is encoded in the lower
// 6 bits of the I-immediate field for RV64I
__ srai(as_Register($dst$$reg),
@ -7455,7 +7418,6 @@ instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
ins_cost(ALU_COST);
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ andr(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg));
@ -7472,7 +7434,6 @@ instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
ins_cost(ALU_COST);
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ andi(as_Register($dst$$reg),
as_Register($src1$$reg),
(int32_t)($src2$$constant));
@ -7489,7 +7450,6 @@ instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
ins_cost(ALU_COST);
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ orr(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg));
@ -7522,7 +7482,6 @@ instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
ins_cost(ALU_COST);
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ xorr(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg));
@ -7555,7 +7514,6 @@ instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
ins_cost(ALU_COST);
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ andr(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg));
@ -7572,7 +7530,6 @@ instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
ins_cost(ALU_COST);
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ andi(as_Register($dst$$reg),
as_Register($src1$$reg),
(int32_t)($src2$$constant));
@ -7589,7 +7546,6 @@ instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
ins_cost(ALU_COST);
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ orr(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg));
@ -7622,7 +7578,6 @@ instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
ins_cost(ALU_COST);
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ xorr(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg));
@ -7824,7 +7779,6 @@ instruct castX2P(iRegPNoSp dst, iRegL src) %{
format %{ "mv $dst, $src\t# long -> ptr, #@castX2P" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
if ($dst$$reg != $src$$reg) {
__ mv(as_Register($dst$$reg), as_Register($src$$reg));
}
@ -7840,7 +7794,6 @@ instruct castP2X(iRegLNoSp dst, iRegP src) %{
format %{ "mv $dst, $src\t# ptr -> long, #@castP2X" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
if ($dst$$reg != $src$$reg) {
__ mv(as_Register($dst$$reg), as_Register($src$$reg));
}
@ -7995,7 +7948,6 @@ instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
format %{ "zero_extend $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ zero_extend(as_Register($dst$$reg), as_Register($src$$reg), 32);
%}
@ -8150,7 +8102,6 @@ instruct convP2I(iRegINoSp dst, iRegP src) %{
format %{ "zero_extend $dst, $src, 32\t# ptr -> int, #@convP2I" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ zero_extend($dst$$Register, $src$$Register, 32);
%}
@ -8168,7 +8119,6 @@ instruct convN2I(iRegINoSp dst, iRegN src)
format %{ "mv $dst, $src\t# compressed ptr -> int, #@convN2I" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ mv($dst$$Register, $src$$Register);
%}
@ -8265,7 +8215,6 @@ instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
format %{ "lw $dst, $src\t#@MoveF2I_stack_reg" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
%}
@ -8302,7 +8251,6 @@ instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
format %{ "ld $dst, $src\t#@MoveD2L_stack_reg" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
%}
@ -8321,7 +8269,6 @@ instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
format %{ "fld $dst, $src\t#@MoveL2D_stack_reg" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
%}
@ -8358,7 +8305,6 @@ instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
format %{ "sw $src, $dst\t#@MoveI2F_reg_stack" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
%}
@ -8377,7 +8323,6 @@ instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
format %{ "fsd $dst, $src\t#@MoveD2L_reg_stack" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
%}
@ -8396,7 +8341,6 @@ instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
format %{ "sd $src, $dst\t#@MoveL2D_reg_stack" %}
ins_encode %{
Assembler::CompressibleRegion cr(&_masm);
__ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
%}