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8332153: RISC-V: enable tests and add comment for vector shift instruct (shared by vectorization and Vector API)

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Reviewed-by: fyang
This commit is contained in:
Hamlin Li 2024-05-21 12:34:06 +00:00
parent ae9ad862ee
commit 5cf8288b80
10 changed files with 176 additions and 3 deletions
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26
src/hotspot/cpu/riscv/riscv_v.ad
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@ -2218,6 +2218,32 @@ instruct replicateD(vReg dst, fRegD src) %{
%}
// vector shift
//
// Following shift instruct's are shared by vectorization (in SLP, superword.cpp) and Vector API.
//
// Shift behaviour in vectorization is defined by java language spec, which includes:
// 1. "If the promoted type of the left-hand operand is int, then only the five lowest-order bits of
// the right-hand operand are used as the shift distance. It is as if the right-hand operand were
// subjected to a bitwise logical AND operator & (§15.22.1) with the mask value 0x1f (0b11111).
// The shift distance actually used is therefore always in the range 0 to 31, inclusive."
// 2. similarly, for long "with the mask value 0x3f (0b111111)"
// check https://docs.oracle.com/javase/specs/jls/se21/html/jls-15.html#jls-15.19 for details.
//
// Shift behaviour in Vector API is defined as:
// e.g. for ASHR, "a>>(n&(ESIZE*8-1))"
// this behaviour is the same as shift instrunction's in riscv vector extension.
// check https://docs.oracle.com/en/java/javase/21/docs/api/jdk.incubator.vector/jdk/incubator/vector/VectorOperators.html#ASHR
// and https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#116-vector-single-width-shift-instructions for details.
//
// Despite the difference between these 2 behaviours, the same shift instruct's of byte and short are
// still shared between vectorization and Vector API. The way it works is hidden inside the implementation
// of vectorization and Vector API:
// 1. when doing optimization vectorization masks the shift value with "(BitsPerInt - 1)" or "(BitsPerLong - 1)"
// 2. in Vector API, shift value is masked with SHIFT_MASK (e.g. for ByteVector it's "Byte.SIZE - 1")
//
// If not because of this pre-processing of shift value respectively in vectorization and Vector API, then
// e.g. for a byte shift value 16, the intrinsic behaviour will be different, and they can not share the same
// instruct here, as vectorization requires x >> 16, but Vector API requires x >> (16 & 7).
instruct vasrB(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{
match(Set dst (RShiftVB src shift));

79
test/hotspot/jtreg/compiler/c2/cr7200264/TestIntVect.java
View File

@ -481,6 +481,9 @@ public class TestIntVect {
@Test
@IR(counts = { IRNode.SUB_VI, "> 0", IRNode.LSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.SUB_VI, "> 0", IRNode.LSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_mulc(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]*VALUE);
@ -490,6 +493,9 @@ public class TestIntVect {
@Test
@IR(counts = { IRNode.SUB_VI, "> 0", IRNode.LSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.SUB_VI, "> 0", IRNode.LSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_mulc_n(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]*(-VALUE));
@ -522,6 +528,14 @@ public class TestIntVect {
IRNode.SUB_VI,
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0" },
applyIfCPUFeatureOr = {"avx2", "true", "sve", "true"})
@IR(counts = { IRNode.ADD_VI,
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0",
IRNode.RSHIFT_VI,
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0",
IRNode.SUB_VI,
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
// Not vectorized: On aarch64, vectorization for this example results in
// MulVL nodes, which asimd does not support.
@IR(counts = { IRNode.LOAD_VECTOR_I, "= 0",
@ -542,6 +556,14 @@ public class TestIntVect {
IRNode.SUB_VI,
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0" },
applyIfCPUFeatureOr = {"avx2", "true", "sve", "true"})
@IR(counts = { IRNode.ADD_VI,
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0",
IRNode.RSHIFT_VI,
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0",
IRNode.SUB_VI,
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
// Not vectorized: On aarch64, vectorization for this example results in
// MulVL nodes, which asimd does not support.
@IR(counts = { IRNode.LOAD_VECTOR_I, "= 0",
@ -662,6 +684,9 @@ public class TestIntVect {
@Test
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_sllc(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]<<VALUE);
@ -671,6 +696,9 @@ public class TestIntVect {
@Test
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_sllc_n(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]<<(-VALUE));
@ -683,6 +711,11 @@ public class TestIntVect {
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.LSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_sllc_o(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]<<SHIFT);
@ -695,6 +728,11 @@ public class TestIntVect {
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.LSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_sllc_on(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]<<(-SHIFT));
@ -704,6 +742,9 @@ public class TestIntVect {
@Test
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_sllv(int[] a0, int[] a1, int b) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]<<b);
@ -713,6 +754,9 @@ public class TestIntVect {
@Test
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_srlc(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>>VALUE);
@ -722,6 +766,9 @@ public class TestIntVect {
@Test
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_srlc_n(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>>(-VALUE));
@ -734,6 +781,11 @@ public class TestIntVect {
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.URSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_srlc_o(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>>SHIFT);
@ -746,6 +798,11 @@ public class TestIntVect {
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.URSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_srlc_on(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>>(-SHIFT));
@ -755,6 +812,9 @@ public class TestIntVect {
@Test
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_srlv(int[] a0, int[] a1, int b) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>>b);
@ -764,6 +824,9 @@ public class TestIntVect {
@Test
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_srac(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>VALUE);
@ -773,6 +836,9 @@ public class TestIntVect {
@Test
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_srac_n(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>(-VALUE));
@ -785,6 +851,11 @@ public class TestIntVect {
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.RSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_srac_o(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>SHIFT);
@ -797,6 +868,11 @@ public class TestIntVect {
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.RSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_srac_on(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>(-SHIFT));
@ -806,6 +882,9 @@ public class TestIntVect {
@Test
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
void test_srav(int[] a0, int[] a1, int b) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>b);

3
test/hotspot/jtreg/compiler/c2/irTests/TestVectorizeURShiftSubword.java
View File

@ -34,7 +34,8 @@ import jdk.test.lib.Utils;
* @bug 8283307
* @key randomness
* @summary Auto-vectorization enhancement for unsigned shift right on signed subword types
* @requires ((os.arch=="amd64" | os.arch=="x86_64") & (vm.opt.UseSSE == "null" | vm.opt.UseSSE > 3)) | os.arch=="aarch64"
* @requires ((os.arch=="amd64" | os.arch=="x86_64") & (vm.opt.UseSSE == "null" | vm.opt.UseSSE > 3)) | os.arch=="aarch64" |
* (os.arch == "riscv64" & vm.cpu.features ~= ".*v,.*")
* @library /test/lib /
* @run driver compiler.c2.irTests.TestVectorizeURShiftSubword
*/

1
test/hotspot/jtreg/compiler/lib/ir_framework/test/IREncodingPrinter.java
View File

@ -104,6 +104,7 @@ public class IREncodingPrinter {
"asimd",
"sve",
// Riscv64
"v",
"zvbb"
));

23
test/hotspot/jtreg/compiler/vectorization/runner/ArrayShiftOpTest.java
View File

@ -35,7 +35,7 @@
* -XX:+WhiteBoxAPI
* compiler.vectorization.runner.ArrayShiftOpTest
*
* @requires (os.simpleArch == "x64") | (os.simpleArch == "aarch64")
* @requires (os.simpleArch == "x64") | (os.simpleArch == "aarch64") | (os.simpleArch == "riscv64")
* @requires vm.compiler2.enabled
*/
@ -99,6 +99,9 @@ public class ArrayShiftOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.RSHIFT_VI, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.RSHIFT_VI, ">0"})
public int[] intShiftLargeDistConstant() {
int[] res = new int[SIZE];
for (int i = 0; i < SIZE; i++) {
@ -110,6 +113,9 @@ public class ArrayShiftOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.RSHIFT_VI, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.RSHIFT_VI, ">0"})
public int[] intShiftLargeDistInvariant() {
int[] res = new int[SIZE];
for (int i = 0; i < SIZE; i++) {
@ -121,6 +127,9 @@ public class ArrayShiftOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.RSHIFT_VS, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.RSHIFT_VS, ">0"})
public short[] shortShiftLargeDistConstant() {
short[] res = new short[SIZE];
for (int i = 0; i < SIZE; i++) {
@ -132,6 +141,9 @@ public class ArrayShiftOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.RSHIFT_VS, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.RSHIFT_VS, ">0"})
public short[] shortShiftLargeDistInvariant() {
short[] res = new short[SIZE];
for (int i = 0; i < SIZE; i++) {
@ -143,6 +155,9 @@ public class ArrayShiftOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.LSHIFT_VL, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.LSHIFT_VL, ">0"})
public long[] longShiftLargeDistConstant() {
long[] res = new long[SIZE];
for (int i = 0; i < SIZE; i++) {
@ -154,6 +169,9 @@ public class ArrayShiftOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.URSHIFT_VL, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.URSHIFT_VL, ">0"})
public long[] longShiftLargeDistInvariant() {
long[] res = new long[SIZE];
for (int i = 0; i < SIZE; i++) {
@ -187,6 +205,9 @@ public class ArrayShiftOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.RSHIFT_VS, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.RSHIFT_VS, ">0"})
public short[] vectorUnsignedShiftRight() {
short[] res = new short[SIZE];
for (int i = 0; i < SIZE; i++) {

9
test/hotspot/jtreg/compiler/vectorization/runner/BasicByteOpTest.java
View File

@ -191,6 +191,9 @@ public class BasicByteOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"},
counts = {IRNode.LSHIFT_VB, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.LSHIFT_VB, ">0"})
public byte[] vectorShiftLeft() {
byte[] res = new byte[SIZE];
for (int i = 0; i < SIZE; i++) {
@ -202,6 +205,9 @@ public class BasicByteOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"},
counts = {IRNode.RSHIFT_VB, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.RSHIFT_VB, ">0"})
public byte[] vectorSignedShiftRight() {
byte[] res = new byte[SIZE];
for (int i = 0; i < SIZE; i++) {
@ -213,6 +219,9 @@ public class BasicByteOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"},
counts = {IRNode.RSHIFT_VB, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.RSHIFT_VB, ">0"})
public byte[] vectorUnsignedShiftRight() {
byte[] res = new byte[SIZE];
for (int i = 0; i < SIZE; i++) {

9
test/hotspot/jtreg/compiler/vectorization/runner/BasicCharOpTest.java
View File

@ -193,6 +193,9 @@ public class BasicCharOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.LSHIFT_VC, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.LSHIFT_VC, ">0"})
public char[] vectorShiftLeft() {
char[] res = new char[SIZE];
for (int i = 0; i < SIZE; i++) {
@ -204,6 +207,9 @@ public class BasicCharOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.URSHIFT_VC, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.URSHIFT_VC, ">0"})
public char[] vectorSignedShiftRight() {
char[] res = new char[SIZE];
for (int i = 0; i < SIZE; i++) {
@ -215,6 +221,9 @@ public class BasicCharOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.URSHIFT_VC, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.URSHIFT_VC, ">0"})
public char[] vectorUnsignedShiftRight() {
char[] res = new char[SIZE];
for (int i = 0; i < SIZE; i++) {

9
test/hotspot/jtreg/compiler/vectorization/runner/BasicIntOpTest.java
View File

@ -200,6 +200,9 @@ public class BasicIntOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.LSHIFT_VI, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.LSHIFT_VI, ">0"})
public int[] vectorShiftLeft() {
int[] res = new int[SIZE];
for (int i = 0; i < SIZE; i++) {
@ -211,6 +214,9 @@ public class BasicIntOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.RSHIFT_VI, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.RSHIFT_VI, ">0"})
public int[] vectorSignedShiftRight() {
int[] res = new int[SIZE];
for (int i = 0; i < SIZE; i++) {
@ -222,6 +228,9 @@ public class BasicIntOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.URSHIFT_VI, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.URSHIFT_VI, ">0"})
public int[] vectorUnsignedShiftRight() {
int[] res = new int[SIZE];
for (int i = 0; i < SIZE; i++) {

11
test/hotspot/jtreg/compiler/vectorization/runner/BasicLongOpTest.java
View File

@ -36,7 +36,7 @@
* -XX:+WhiteBoxAPI
* compiler.vectorization.runner.BasicLongOpTest
*
* @requires (os.simpleArch == "x64") | (os.simpleArch == "aarch64")
* @requires (os.simpleArch == "x64") | (os.simpleArch == "aarch64") | (os.simpleArch == "riscv64")
* @requires vm.compiler2.enabled
*/
@ -192,6 +192,9 @@ public class BasicLongOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.LSHIFT_VL, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.LSHIFT_VL, ">0"})
public long[] vectorShiftLeft() {
long[] res = new long[SIZE];
for (int i = 0; i < SIZE; i++) {
@ -203,6 +206,9 @@ public class BasicLongOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.RSHIFT_VL, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.RSHIFT_VL, ">0"})
public long[] vectorSignedShiftRight() {
long[] res = new long[SIZE];
for (int i = 0; i < SIZE; i++) {
@ -214,6 +220,9 @@ public class BasicLongOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.URSHIFT_VL, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.URSHIFT_VL, ">0"})
public long[] vectorUnsignedShiftRight() {
long[] res = new long[SIZE];
for (int i = 0; i < SIZE; i++) {

9
test/hotspot/jtreg/compiler/vectorization/runner/BasicShortOpTest.java
View File

@ -191,6 +191,9 @@ public class BasicShortOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.LSHIFT_VS, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.LSHIFT_VS, ">0"})
public short[] vectorShiftLeft() {
short[] res = new short[SIZE];
for (int i = 0; i < SIZE; i++) {
@ -202,6 +205,9 @@ public class BasicShortOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.RSHIFT_VS, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.RSHIFT_VS, ">0"})
public short[] vectorSignedShiftRight() {
short[] res = new short[SIZE];
for (int i = 0; i < SIZE; i++) {
@ -238,6 +244,9 @@ public class BasicShortOpTest extends VectorizationTestRunner {
@Test
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
counts = {IRNode.RSHIFT_VS, ">0"})
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {IRNode.RSHIFT_VS, ">0"})
public short[] vectorUnsignedShiftRight() {
short[] res = new short[SIZE];
for (int i = 0; i < SIZE; i++) {