8217856: ZGC: Break out C2 matching rules into separate AD file
Reviewed-by: neliasso, kvn
This commit is contained in:
Per Lidén
parent
9f3059e20c
commit
667bba8e95
@ -1,5 +1,5 @@
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#
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# Copyright (c) 2013, 2018, Oracle and/or its affiliates. All rights reserved.
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# Copyright (c) 2013, 2019, Oracle and/or its affiliates. All rights reserved.
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# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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#
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# This code is free software; you can redistribute it and/or modify it
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@ -142,6 +142,12 @@ ifeq ($(call check-jvm-feature, compiler2), true)
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)))
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endif
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ifeq ($(call check-jvm-feature, zgc), true)
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AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \
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$d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/gc/z/z_$(HOTSPOT_TARGET_CPU).ad \
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)))
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endif
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SINGLE_AD_SRCFILE := $(ADLC_SUPPORT_DIR)/all-ad-src.ad
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INSERT_FILENAME_AWK_SCRIPT := \
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155
src/hotspot/cpu/x86/gc/z/z_x86_64.ad
Normal file
155
src/hotspot/cpu/x86/gc/z/z_x86_64.ad
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@ -0,0 +1,155 @@
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//
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// Copyright (c) 2015, 2019, Oracle and/or its affiliates. All rights reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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//
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// This code is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License version 2 only, as
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// published by the Free Software Foundation.
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//
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// This code is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// version 2 for more details (a copy is included in the LICENSE file that
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// accompanied this code).
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//
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// You should have received a copy of the GNU General Public License version
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// 2 along with this work; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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//
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// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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// or visit www.oracle.com if you need additional information or have any
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// questions.
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//
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source %{
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#include "gc/z/zBarrierSetAssembler.hpp"
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static void z_load_barrier_slow_reg(MacroAssembler& _masm, Register dst, Address src, bool weak) {
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assert(dst != r12, "Invalid register");
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assert(dst != r15, "Invalid register");
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assert(dst != rsp, "Invalid register");
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const address stub = weak ? ZBarrierSet::assembler()->load_barrier_weak_slow_stub(dst)
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: ZBarrierSet::assembler()->load_barrier_slow_stub(dst);
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__ lea(dst, src);
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__ call(RuntimeAddress(stub));
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}
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%}
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// For XMM and YMM enabled processors
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instruct zLoadBarrierSlowRegXmmAndYmm(rRegP dst, memory src, rFlagsReg cr,
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rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
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rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
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rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
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rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
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match(Set dst (LoadBarrierSlowReg src));
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predicate(UseAVX <= 2);
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effect(DEF dst, KILL cr,
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KILL x0, KILL x1, KILL x2, KILL x3,
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KILL x4, KILL x5, KILL x6, KILL x7,
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KILL x8, KILL x9, KILL x10, KILL x11,
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KILL x12, KILL x13, KILL x14, KILL x15);
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format %{ "zLoadBarrierSlowRegXmmAndYmm $dst, $src" %}
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ins_encode %{
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z_load_barrier_slow_reg(_masm, $dst$$Register, $src$$Address, false /* weak */);
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%}
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ins_pipe(pipe_slow);
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%}
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// For ZMM enabled processors
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instruct zLoadBarrierSlowRegZmm(rRegP dst, memory src, rFlagsReg cr,
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rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
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rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
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rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
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rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15,
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rxmm16 x16, rxmm17 x17, rxmm18 x18, rxmm19 x19,
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rxmm20 x20, rxmm21 x21, rxmm22 x22, rxmm23 x23,
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rxmm24 x24, rxmm25 x25, rxmm26 x26, rxmm27 x27,
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rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
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match(Set dst (LoadBarrierSlowReg src));
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predicate(UseAVX == 3);
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effect(DEF dst, KILL cr,
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KILL x0, KILL x1, KILL x2, KILL x3,
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KILL x4, KILL x5, KILL x6, KILL x7,
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KILL x8, KILL x9, KILL x10, KILL x11,
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KILL x12, KILL x13, KILL x14, KILL x15,
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KILL x16, KILL x17, KILL x18, KILL x19,
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KILL x20, KILL x21, KILL x22, KILL x23,
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KILL x24, KILL x25, KILL x26, KILL x27,
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KILL x28, KILL x29, KILL x30, KILL x31);
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format %{ "zLoadBarrierSlowRegZmm $dst, $src" %}
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ins_encode %{
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z_load_barrier_slow_reg(_masm, $dst$$Register, $src$$Address, false /* weak */);
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%}
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ins_pipe(pipe_slow);
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%}
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// For XMM and YMM enabled processors
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instruct zLoadBarrierWeakSlowRegXmmAndYmm(rRegP dst, memory src, rFlagsReg cr,
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rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
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rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
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rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
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rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
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match(Set dst (LoadBarrierWeakSlowReg src));
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predicate(UseAVX <= 2);
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effect(DEF dst, KILL cr,
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KILL x0, KILL x1, KILL x2, KILL x3,
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KILL x4, KILL x5, KILL x6, KILL x7,
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KILL x8, KILL x9, KILL x10, KILL x11,
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KILL x12, KILL x13, KILL x14, KILL x15);
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format %{ "zLoadBarrierWeakSlowRegXmmAndYmm $dst, $src" %}
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ins_encode %{
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z_load_barrier_slow_reg(_masm, $dst$$Register, $src$$Address, true /* weak */);
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%}
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ins_pipe(pipe_slow);
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%}
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// For ZMM enabled processors
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instruct zLoadBarrierWeakSlowRegZmm(rRegP dst, memory src, rFlagsReg cr,
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rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
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rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
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rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
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rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15,
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rxmm16 x16, rxmm17 x17, rxmm18 x18, rxmm19 x19,
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rxmm20 x20, rxmm21 x21, rxmm22 x22, rxmm23 x23,
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rxmm24 x24, rxmm25 x25, rxmm26 x26, rxmm27 x27,
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rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
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match(Set dst (LoadBarrierWeakSlowReg src));
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predicate(UseAVX == 3);
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effect(DEF dst, KILL cr,
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KILL x0, KILL x1, KILL x2, KILL x3,
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KILL x4, KILL x5, KILL x6, KILL x7,
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KILL x8, KILL x9, KILL x10, KILL x11,
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KILL x12, KILL x13, KILL x14, KILL x15,
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KILL x16, KILL x17, KILL x18, KILL x19,
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KILL x20, KILL x21, KILL x22, KILL x23,
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KILL x24, KILL x25, KILL x26, KILL x27,
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KILL x28, KILL x29, KILL x30, KILL x31);
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format %{ "zLoadBarrierWeakSlowRegZmm $dst, $src" %}
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ins_encode %{
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z_load_barrier_slow_reg(_masm, $dst$$Register, $src$$Address, true /* weak */);
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%}
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ins_pipe(pipe_slow);
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%}
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@ -1,5 +1,5 @@
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//
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// Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved.
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// Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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//
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// This code is free software; you can redistribute it and/or modify it
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@ -526,12 +526,6 @@ reg_class int_rdi_reg(RDI);
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%}
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source_hpp %{
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#if INCLUDE_ZGC
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#include "gc/z/zBarrierSetAssembler.hpp"
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#endif
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%}
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//----------SOURCE BLOCK-------------------------------------------------------
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// This is a block of C++ code which provides values, functions, and
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// definitions necessary in the rest of the architecture description
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@ -12711,170 +12705,6 @@ instruct RethrowException()
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ins_pipe(pipe_jmp);
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%}
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//
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// Execute ZGC load barrier (strong) slow path
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//
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// For XMM and YMM enabled processors
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instruct loadBarrierSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
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rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
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rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
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rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
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rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
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match(Set dst (LoadBarrierSlowReg mem));
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predicate(UseAVX <= 2);
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effect(DEF dst, KILL cr,
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KILL x0, KILL x1, KILL x2, KILL x3,
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KILL x4, KILL x5, KILL x6, KILL x7,
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KILL x8, KILL x9, KILL x10, KILL x11,
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KILL x12, KILL x13, KILL x14, KILL x15);
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format %{"LoadBarrierSlowRegXmmAndYmm $dst, $mem" %}
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ins_encode %{
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#if INCLUDE_ZGC
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Register d = $dst$$Register;
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ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
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assert(d != r12, "Can't be R12!");
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assert(d != r15, "Can't be R15!");
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assert(d != rsp, "Can't be RSP!");
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__ lea(d, $mem$$Address);
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__ call(RuntimeAddress(bs->load_barrier_slow_stub(d)));
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#else
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ShouldNotReachHere();
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#endif
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%}
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ins_pipe(pipe_slow);
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%}
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// For ZMM enabled processors
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instruct loadBarrierSlowRegZmm(rRegP dst, memory mem, rFlagsReg cr,
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rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
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rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
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rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
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rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15,
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rxmm16 x16, rxmm17 x17, rxmm18 x18, rxmm19 x19,
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rxmm20 x20, rxmm21 x21, rxmm22 x22, rxmm23 x23,
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rxmm24 x24, rxmm25 x25, rxmm26 x26, rxmm27 x27,
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rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
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match(Set dst (LoadBarrierSlowReg mem));
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predicate(UseAVX == 3);
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effect(DEF dst, KILL cr,
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KILL x0, KILL x1, KILL x2, KILL x3,
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KILL x4, KILL x5, KILL x6, KILL x7,
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KILL x8, KILL x9, KILL x10, KILL x11,
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KILL x12, KILL x13, KILL x14, KILL x15,
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KILL x16, KILL x17, KILL x18, KILL x19,
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KILL x20, KILL x21, KILL x22, KILL x23,
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KILL x24, KILL x25, KILL x26, KILL x27,
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KILL x28, KILL x29, KILL x30, KILL x31);
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format %{"LoadBarrierSlowRegZmm $dst, $mem" %}
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ins_encode %{
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#if INCLUDE_ZGC
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Register d = $dst$$Register;
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ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
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assert(d != r12, "Can't be R12!");
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assert(d != r15, "Can't be R15!");
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assert(d != rsp, "Can't be RSP!");
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__ lea(d, $mem$$Address);
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__ call(RuntimeAddress(bs->load_barrier_slow_stub(d)));
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#else
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ShouldNotReachHere();
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#endif
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%}
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ins_pipe(pipe_slow);
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%}
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//
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// Execute ZGC load barrier (weak) slow path
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//
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// For XMM and YMM enabled processors
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instruct loadBarrierWeakSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
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rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
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rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
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rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
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rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
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match(Set dst (LoadBarrierWeakSlowReg mem));
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predicate(UseAVX <= 2);
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effect(DEF dst, KILL cr,
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KILL x0, KILL x1, KILL x2, KILL x3,
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KILL x4, KILL x5, KILL x6, KILL x7,
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KILL x8, KILL x9, KILL x10, KILL x11,
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KILL x12, KILL x13, KILL x14, KILL x15);
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format %{"LoadBarrierWeakSlowRegXmmAndYmm $dst, $mem" %}
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ins_encode %{
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#if INCLUDE_ZGC
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Register d = $dst$$Register;
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ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
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assert(d != r12, "Can't be R12!");
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assert(d != r15, "Can't be R15!");
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assert(d != rsp, "Can't be RSP!");
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__ lea(d,$mem$$Address);
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__ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d)));
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#else
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ShouldNotReachHere();
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#endif
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%}
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ins_pipe(pipe_slow);
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%}
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// For ZMM enabled processors
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instruct loadBarrierWeakSlowRegZmm(rRegP dst, memory mem, rFlagsReg cr,
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rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
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rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
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rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
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rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15,
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rxmm16 x16, rxmm17 x17, rxmm18 x18, rxmm19 x19,
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rxmm20 x20, rxmm21 x21, rxmm22 x22, rxmm23 x23,
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rxmm24 x24, rxmm25 x25, rxmm26 x26, rxmm27 x27,
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rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
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match(Set dst (LoadBarrierWeakSlowReg mem));
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predicate(UseAVX == 3);
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effect(DEF dst, KILL cr,
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KILL x0, KILL x1, KILL x2, KILL x3,
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KILL x4, KILL x5, KILL x6, KILL x7,
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KILL x8, KILL x9, KILL x10, KILL x11,
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KILL x12, KILL x13, KILL x14, KILL x15,
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KILL x16, KILL x17, KILL x18, KILL x19,
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KILL x20, KILL x21, KILL x22, KILL x23,
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KILL x24, KILL x25, KILL x26, KILL x27,
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KILL x28, KILL x29, KILL x30, KILL x31);
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format %{"LoadBarrierWeakSlowRegZmm $dst, $mem" %}
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ins_encode %{
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#if INCLUDE_ZGC
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Register d = $dst$$Register;
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ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
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assert(d != r12, "Can't be R12!");
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assert(d != r15, "Can't be R15!");
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assert(d != rsp, "Can't be RSP!");
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__ lea(d,$mem$$Address);
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__ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d)));
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#else
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ShouldNotReachHere();
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#endif
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%}
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ins_pipe(pipe_slow);
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%}
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// ============================================================================
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// This name is KNOWN by the ADLC and cannot be changed.
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// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
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