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8144587: aarch64: generate vectorized MLA/MLS instructions

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Add support for MLA/MLS (vector) instructions

Reviewed-by: roland
This commit is contained in:
Fei Yang 2015-12-07 21:23:02 +08:00
parent 43d48c16d2
commit 67caeeaa08
2 changed files with 120 additions and 0 deletions
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118
hotspot/src/cpu/aarch64/vm/aarch64.ad
View File

@ -15318,6 +15318,124 @@ instruct vmul2D(vecX dst, vecX src1, vecX src2)
ins_pipe(pipe_class_default);
%}
// --------------------------------- MLA --------------------------------------
instruct vmla4S(vecD dst, vecD src1, vecD src2)
%{
predicate(n->as_Vector()->length() == 2 ||
n->as_Vector()->length() == 4);
match(Set dst (AddVS dst (MulVS src1 src2)));
ins_cost(INSN_COST);
format %{ "mlav $dst,$src1,$src2\t# vector (4H)" %}
ins_encode %{
__ mlav(as_FloatRegister($dst$$reg), __ T4H,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_class_default);
%}
instruct vmla8S(vecX dst, vecX src1, vecX src2)
%{
predicate(n->as_Vector()->length() == 8);
match(Set dst (AddVS dst (MulVS src1 src2)));
ins_cost(INSN_COST);
format %{ "mlav $dst,$src1,$src2\t# vector (8H)" %}
ins_encode %{
__ mlav(as_FloatRegister($dst$$reg), __ T8H,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_class_default);
%}
instruct vmla2I(vecD dst, vecD src1, vecD src2)
%{
predicate(n->as_Vector()->length() == 2);
match(Set dst (AddVI dst (MulVI src1 src2)));
ins_cost(INSN_COST);
format %{ "mlav $dst,$src1,$src2\t# vector (2S)" %}
ins_encode %{
__ mlav(as_FloatRegister($dst$$reg), __ T2S,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_class_default);
%}
instruct vmla4I(vecX dst, vecX src1, vecX src2)
%{
predicate(n->as_Vector()->length() == 4);
match(Set dst (AddVI dst (MulVI src1 src2)));
ins_cost(INSN_COST);
format %{ "mlav $dst,$src1,$src2\t# vector (4S)" %}
ins_encode %{
__ mlav(as_FloatRegister($dst$$reg), __ T4S,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_class_default);
%}
// --------------------------------- MLS --------------------------------------
instruct vmls4S(vecD dst, vecD src1, vecD src2)
%{
predicate(n->as_Vector()->length() == 2 ||
n->as_Vector()->length() == 4);
match(Set dst (SubVS dst (MulVS src1 src2)));
ins_cost(INSN_COST);
format %{ "mlsv $dst,$src1,$src2\t# vector (4H)" %}
ins_encode %{
__ mlsv(as_FloatRegister($dst$$reg), __ T4H,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_class_default);
%}
instruct vmls8S(vecX dst, vecX src1, vecX src2)
%{
predicate(n->as_Vector()->length() == 8);
match(Set dst (SubVS dst (MulVS src1 src2)));
ins_cost(INSN_COST);
format %{ "mlsv $dst,$src1,$src2\t# vector (8H)" %}
ins_encode %{
__ mlsv(as_FloatRegister($dst$$reg), __ T8H,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_class_default);
%}
instruct vmls2I(vecD dst, vecD src1, vecD src2)
%{
predicate(n->as_Vector()->length() == 2);
match(Set dst (SubVI dst (MulVI src1 src2)));
ins_cost(INSN_COST);
format %{ "mlsv $dst,$src1,$src2\t# vector (2S)" %}
ins_encode %{
__ mlsv(as_FloatRegister($dst$$reg), __ T2S,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_class_default);
%}
instruct vmls4I(vecX dst, vecX src1, vecX src2)
%{
predicate(n->as_Vector()->length() == 4);
match(Set dst (SubVI dst (MulVI src1 src2)));
ins_cost(INSN_COST);
format %{ "mlsv $dst,$src1,$src2\t# vector (4S)" %}
ins_encode %{
__ mlsv(as_FloatRegister($dst$$reg), __ T4S,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_class_default);
%}
// --------------------------------- DIV --------------------------------------
instruct vdiv2F(vecD dst, vecD src1, vecD src2)

2
hotspot/src/cpu/aarch64/vm/assembler_aarch64.hpp
View File

@ -2041,6 +2041,8 @@ public:
INSN(addv, 0, 0b100001);
INSN(subv, 1, 0b100001);
INSN(mulv, 0, 0b100111);
INSN(mlav, 0, 0b100101);
INSN(mlsv, 1, 0b100101);
INSN(sshl, 0, 0b010001);
INSN(ushl, 1, 0b010001);