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This commit is contained in:
Jesper Wilhelmsson 2022-01-13 01:05:45 +00:00
commit 67e3d51d68
16 changed files with 886 additions and 96 deletions
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11
src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp
View File

@ -1783,13 +1783,14 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
// Simple recursive lock?
__ ldr(rscratch1, Address(sp, lock_slot_offset * VMRegImpl::stack_slot_size));
__ cbz(rscratch1, done);
}
// Must save r0 if if it is live now because cmpxchg must use it
if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
save_native_result(masm, ret_type, stack_slots);
}
// Must save r0 if if it is live now because cmpxchg must use it
if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
save_native_result(masm, ret_type, stack_slots);
}
if (!UseHeavyMonitors) {
// get address of the stack lock
__ lea(r0, Address(sp, lock_slot_offset * VMRegImpl::stack_slot_size));
// get old displaced header

431
src/hotspot/cpu/arm/arm.ad
View File

@ -1,5 +1,5 @@
//
// Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
@ -123,9 +123,18 @@ public:
};
};
// Assert that the given node is not a var shift.
bool assert_not_var_shift(const Node *n);
%}
source %{
// Assert that the given node is not a var shift.
bool assert_not_var_shift(const Node *n) {
assert(!n->as_ShiftV()->is_var_shift(), "illegal var shift");
return true;
}
#define __ _masm.
static FloatRegister reg_to_FloatRegister_object(int register_encoding);
@ -10591,7 +10600,7 @@ instruct vneg16B_reg(vecX dst, vecX src) %{
ins_pipe( ialu_reg_reg ); // FIXME
%}
// ------------------------------ Shift ---------------------------------------
// ------------------------------ ShiftCount ----------------------------------
instruct vslcntD(vecD dst, iRegI cnt) %{
predicate(n->as_Vector()->length_in_bytes() == 8 && VM_Version::has_simd());
@ -10650,6 +10659,8 @@ instruct vsrcntX(vecX dst, iRegI cnt) %{
ins_pipe( ialu_reg_reg ); // FIXME
%}
// ------------------------------ LogicalShift --------------------------------
// Byte vector logical left/right shift based on sign
instruct vsh8B_reg(vecD dst, vecD src, vecD shift) %{
predicate(n->as_Vector()->length() == 8);
@ -10766,9 +10777,9 @@ instruct vsh2L_reg(vecX dst, vecX src, vecX shift) %{
ins_pipe( ialu_reg_reg ); // FIXME
%}
// ------------------------------ LeftShift -----------------------------------
// ------------------------------ LogicalLeftShift ----------------------------
// Byte vector left shift
// Byte vector logical left shift
instruct vsl8B_reg(vecD dst, vecD src, vecD shift) %{
predicate(n->as_Vector()->length() == 8);
match(Set dst (LShiftVB src shift));
@ -10790,7 +10801,7 @@ instruct vsl16B_reg(vecX dst, vecX src, vecX shift) %{
%}
instruct vsl8B_immI(vecD dst, vecD src, immI shift) %{
predicate(n->as_Vector()->length() == 8);
predicate(n->as_Vector()->length() == 8 && assert_not_var_shift(n));
match(Set dst (LShiftVB src (LShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -10806,7 +10817,7 @@ instruct vsl8B_immI(vecD dst, vecD src, immI shift) %{
%}
instruct vsl16B_immI(vecX dst, vecX src, immI shift) %{
predicate(n->as_Vector()->length() == 16);
predicate(n->as_Vector()->length() == 16 && assert_not_var_shift(n));
match(Set dst (LShiftVB src (LShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -10821,11 +10832,10 @@ instruct vsl16B_immI(vecX dst, vecX src, immI shift) %{
ins_pipe( ialu_reg_reg ); // FIXME
%}
// Shorts/Chars vector logical left/right shift
// Shorts/Chars vector logical left shift
instruct vsl4S_reg(vecD dst, vecD src, vecD shift) %{
predicate(n->as_Vector()->length() == 4);
match(Set dst (LShiftVS src shift));
match(Set dst (URShiftVS src shift));
size(4*1);
ins_cost(DEFAULT_COST*1); // FIXME
expand %{
@ -10836,7 +10846,6 @@ instruct vsl4S_reg(vecD dst, vecD src, vecD shift) %{
instruct vsl8S_reg(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 8);
match(Set dst (LShiftVS src shift));
match(Set dst (URShiftVS src shift));
size(4*1);
ins_cost(DEFAULT_COST*1); // FIXME
expand %{
@ -10845,7 +10854,7 @@ instruct vsl8S_reg(vecX dst, vecX src, vecX shift) %{
%}
instruct vsl4S_immI(vecD dst, vecD src, immI shift) %{
predicate(n->as_Vector()->length() == 4);
predicate(n->as_Vector()->length() == 4 && assert_not_var_shift(n));
match(Set dst (LShiftVS src (LShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -10861,7 +10870,7 @@ instruct vsl4S_immI(vecD dst, vecD src, immI shift) %{
%}
instruct vsl8S_immI(vecX dst, vecX src, immI shift) %{
predicate(n->as_Vector()->length() == 8);
predicate(n->as_Vector()->length() == 8 && assert_not_var_shift(n));
match(Set dst (LShiftVS src shift));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -10876,11 +10885,10 @@ instruct vsl8S_immI(vecX dst, vecX src, immI shift) %{
ins_pipe( ialu_reg_reg ); // FIXME
%}
// Integers vector logical left/right shift
// Integers vector logical left shift
instruct vsl2I_reg(vecD dst, vecD src, vecD shift) %{
predicate(n->as_Vector()->length() == 2 && VM_Version::has_simd());
match(Set dst (LShiftVI src shift));
match(Set dst (URShiftVI src shift));
size(4*1);
ins_cost(DEFAULT_COST*1); // FIXME
expand %{
@ -10891,7 +10899,6 @@ instruct vsl2I_reg(vecD dst, vecD src, vecD shift) %{
instruct vsl4I_reg(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 4 && VM_Version::has_simd());
match(Set dst (LShiftVI src shift));
match(Set dst (URShiftVI src shift));
size(4*1);
ins_cost(DEFAULT_COST*1); // FIXME
expand %{
@ -10900,7 +10907,9 @@ instruct vsl4I_reg(vecX dst, vecX src, vecX shift) %{
%}
instruct vsl2I_immI(vecD dst, vecD src, immI shift) %{
predicate(n->as_Vector()->length() == 2 && VM_Version::has_simd());
predicate(n->as_Vector()->length() == 2 &&
VM_Version::has_simd() &&
assert_not_var_shift(n));
match(Set dst (LShiftVI src (LShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -10916,7 +10925,9 @@ instruct vsl2I_immI(vecD dst, vecD src, immI shift) %{
%}
instruct vsl4I_immI(vecX dst, vecX src, immI shift) %{
predicate(n->as_Vector()->length() == 4 && VM_Version::has_simd());
predicate(n->as_Vector()->length() == 4 &&
VM_Version::has_simd() &&
assert_not_var_shift(n));
match(Set dst (LShiftVI src (LShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -10931,11 +10942,10 @@ instruct vsl4I_immI(vecX dst, vecX src, immI shift) %{
ins_pipe( ialu_reg_reg ); // FIXME
%}
// Longs vector logical left/right shift
// Longs vector logical left shift
instruct vsl2L_reg(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (LShiftVL src shift));
match(Set dst (URShiftVL src shift));
size(4*1);
ins_cost(DEFAULT_COST*1); // FIXME
expand %{
@ -10944,7 +10954,7 @@ instruct vsl2L_reg(vecX dst, vecX src, vecX shift) %{
%}
instruct vsl2L_immI(vecX dst, vecX src, immI shift) %{
predicate(n->as_Vector()->length() == 2);
predicate(n->as_Vector()->length() == 2 && assert_not_var_shift(n));
match(Set dst (LShiftVL src (LShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -10965,9 +10975,79 @@ instruct vsl2L_immI(vecX dst, vecX src, immI shift) %{
// for negative data because java code convert short value into int with
// sign extension before a shift.
// Right shift with vector shift count on aarch32 SIMD is implemented as left
// shift by negative shift count value.
//
// Method is_var_shift() denotes that vector shift count is a variable shift:
// 1) for this case, vector shift count should be negated before conducting
// right shifts. E.g., vsrl4S_reg_var rule.
// 2) for the opposite case, vector shift count is generated via RShiftCntV
// rules and is already negated there. Hence, no negation is needed.
// E.g., vsrl4S_reg rule.
// Chars vector logical right shift
instruct vsrl4S_reg(vecD dst, vecD src, vecD shift) %{
predicate(n->as_Vector()->length() == 4 && !n->as_ShiftV()->is_var_shift());
match(Set dst (URShiftVS src shift));
size(4);
ins_cost(DEFAULT_COST);
expand %{
vsh4S_reg(dst, src, shift);
%}
%}
instruct vsrl4S_reg_var(vecD dst, vecD src, vecD shift, vecD tmp) %{
predicate(n->as_Vector()->length() == 4 && n->as_ShiftV()->is_var_shift());
match(Set dst (URShiftVS src shift));
effect(TEMP tmp);
size(4*2);
ins_cost(DEFAULT_COST*2);
format %{
"VNEG.S8 $tmp.D,$shift.D\n\t! neg packed8B"
"VSHL.U16 $dst.D,$src.D,$tmp.D\t! logical right shift packed4S"
%}
ins_encode %{
bool quad = false;
__ vnegI($tmp$$FloatRegister, $shift$$FloatRegister,
MacroAssembler::VELEM_SIZE_8, quad);
__ vshlUI($dst$$FloatRegister, $tmp$$FloatRegister, $src$$FloatRegister,
MacroAssembler::VELEM_SIZE_16, quad);
%}
ins_pipe(ialu_reg_reg);
%}
instruct vsrl8S_reg(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 8 && !n->as_ShiftV()->is_var_shift());
match(Set dst (URShiftVS src shift));
size(4);
ins_cost(DEFAULT_COST);
expand %{
vsh8S_reg(dst, src, shift);
%}
%}
instruct vsrl8S_reg_var(vecX dst, vecX src, vecX shift, vecX tmp) %{
predicate(n->as_Vector()->length() == 8 && n->as_ShiftV()->is_var_shift());
match(Set dst (URShiftVS src shift));
effect(TEMP tmp);
size(4*2);
ins_cost(DEFAULT_COST*2);
format %{
"VNEG.S8 $tmp.Q,$shift.Q\n\t! neg packed16B"
"VSHL.U16 $dst.Q,$src.Q,$tmp.Q\t! logical right shift packed8S"
%}
ins_encode %{
bool quad = true;
__ vnegI($tmp$$FloatRegister, $shift$$FloatRegister,
MacroAssembler::VELEM_SIZE_8, quad);
__ vshlUI($dst$$FloatRegister, $tmp$$FloatRegister, $src$$FloatRegister,
MacroAssembler::VELEM_SIZE_16, quad);
%}
ins_pipe(ialu_reg_reg);
%}
instruct vsrl4S_immI(vecD dst, vecD src, immI shift) %{
predicate(n->as_Vector()->length() == 4);
predicate(n->as_Vector()->length() == 4 && assert_not_var_shift(n));
match(Set dst (URShiftVS src (RShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -10983,7 +11063,7 @@ instruct vsrl4S_immI(vecD dst, vecD src, immI shift) %{
%}
instruct vsrl8S_immI(vecX dst, vecX src, immI shift) %{
predicate(n->as_Vector()->length() == 8);
predicate(n->as_Vector()->length() == 8 && assert_not_var_shift(n));
match(Set dst (URShiftVS src (RShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -10999,8 +11079,78 @@ instruct vsrl8S_immI(vecX dst, vecX src, immI shift) %{
%}
// Integers vector logical right shift
instruct vsrl2I_reg(vecD dst, vecD src, vecD shift) %{
predicate(n->as_Vector()->length() == 2 &&
VM_Version::has_simd() &&
!n->as_ShiftV()->is_var_shift());
match(Set dst (URShiftVI src shift));
size(4);
ins_cost(DEFAULT_COST);
expand %{
vsh2I_reg(dst, src, shift);
%}
%}
instruct vsrl2I_reg_var(vecD dst, vecD src, vecD shift, vecD tmp) %{
predicate(n->as_Vector()->length() == 2 &&
VM_Version::has_simd() &&
n->as_ShiftV()->is_var_shift());
match(Set dst (URShiftVI src shift));
effect(TEMP tmp);
size(4*2);
ins_cost(DEFAULT_COST*2);
format %{
"VNEG.S8 $tmp.D,$shift.D\n\t! neg packed8B"
"VSHL.U32 $dst.D,$src.D,$tmp.D\t! logical right shift packed2I"
%}
ins_encode %{
bool quad = false;
__ vnegI($tmp$$FloatRegister, $shift$$FloatRegister,
MacroAssembler::VELEM_SIZE_8, quad);
__ vshlUI($dst$$FloatRegister, $tmp$$FloatRegister, $src$$FloatRegister,
MacroAssembler::VELEM_SIZE_32, quad);
%}
ins_pipe(ialu_reg_reg);
%}
instruct vsrl4I_reg(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 4 &&
VM_Version::has_simd() &&
!n->as_ShiftV()->is_var_shift());
match(Set dst (URShiftVI src shift));
size(4);
ins_cost(DEFAULT_COST);
expand %{
vsh4I_reg(dst, src, shift);
%}
%}
instruct vsrl4I_reg_var(vecX dst, vecX src, vecX shift, vecX tmp) %{
predicate(n->as_Vector()->length() == 4 &&
VM_Version::has_simd() &&
n->as_ShiftV()->is_var_shift());
match(Set dst (URShiftVI src shift));
effect(TEMP tmp);
size(4*2);
ins_cost(DEFAULT_COST*2);
format %{
"VNEG.S8 $tmp.Q,$shift.Q\n\t! neg packed16B"
"VSHL.U32 $dst.Q,$src.Q,$tmp.Q\t! logical right shift packed4I"
%}
ins_encode %{
bool quad = true;
__ vnegI($tmp$$FloatRegister, $shift$$FloatRegister,
MacroAssembler::VELEM_SIZE_8, quad);
__ vshlUI($dst$$FloatRegister, $tmp$$FloatRegister, $src$$FloatRegister,
MacroAssembler::VELEM_SIZE_32, quad);
%}
ins_pipe(ialu_reg_reg);
%}
instruct vsrl2I_immI(vecD dst, vecD src, immI shift) %{
predicate(n->as_Vector()->length() == 2 && VM_Version::has_simd());
predicate(n->as_Vector()->length() == 2 &&
VM_Version::has_simd() &&
assert_not_var_shift(n));
match(Set dst (URShiftVI src (RShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -11016,7 +11166,9 @@ instruct vsrl2I_immI(vecD dst, vecD src, immI shift) %{
%}
instruct vsrl4I_immI(vecX dst, vecX src, immI shift) %{
predicate(n->as_Vector()->length() == 4 && VM_Version::has_simd());
predicate(n->as_Vector()->length() == 4 &&
VM_Version::has_simd() &&
assert_not_var_shift(n));
match(Set dst (URShiftVI src (RShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -11032,8 +11184,38 @@ instruct vsrl4I_immI(vecX dst, vecX src, immI shift) %{
%}
// Longs vector logical right shift
instruct vsrl2L_reg(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 2 && !n->as_ShiftV()->is_var_shift());
match(Set dst (URShiftVL src shift));
size(4);
ins_cost(DEFAULT_COST);
expand %{
vsh2L_reg(dst, src, shift);
%}
%}
instruct vsrl2L_reg_var(vecX dst, vecX src, vecX shift, vecX tmp) %{
predicate(n->as_Vector()->length() == 2 && n->as_ShiftV()->is_var_shift());
match(Set dst (URShiftVL src shift));
effect(TEMP tmp, DEF dst, USE src, USE shift);
size(4*2);
ins_cost(DEFAULT_COST*2);
format %{
"VNEG.S8 $tmp.Q,$shift.Q\n\t! neg packed16B"
"VSHL.U64 $dst.Q,$src.Q,$tmp.Q\t! logical right shift packed2L"
%}
ins_encode %{
bool quad = true;
__ vnegI($tmp$$FloatRegister, $shift$$FloatRegister,
MacroAssembler::VELEM_SIZE_8, quad);
__ vshlUI($dst$$FloatRegister, $tmp$$FloatRegister, $src$$FloatRegister,
MacroAssembler::VELEM_SIZE_64, quad);
%}
ins_pipe(ialu_reg_reg);
%}
instruct vsrl2L_immI(vecX dst, vecX src, immI shift) %{
predicate(n->as_Vector()->length() == 2);
predicate(n->as_Vector()->length() == 2 && assert_not_var_shift(n));
match(Set dst (URShiftVL src (RShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -11167,9 +11349,8 @@ instruct vsha2L_reg(vecX dst, vecX src, vecX shift) %{
%}
// Byte vector arithmetic right shift
instruct vsra8B_reg(vecD dst, vecD src, vecD shift) %{
predicate(n->as_Vector()->length() == 8);
predicate(n->as_Vector()->length() == 8 && !n->as_ShiftV()->is_var_shift());
match(Set dst (RShiftVB src shift));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -11178,8 +11359,28 @@ instruct vsra8B_reg(vecD dst, vecD src, vecD shift) %{
%}
%}
instruct vsrl16B_reg(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 16);
instruct vsra8B_reg_var(vecD dst, vecD src, vecD shift, vecD tmp) %{
predicate(n->as_Vector()->length() == 8 && n->as_ShiftV()->is_var_shift());
match(Set dst (RShiftVB src shift));
effect(TEMP tmp);
size(4*2);
ins_cost(DEFAULT_COST*2);
format %{
"VNEG.S8 $tmp.D,$shift.D\n\t! neg packed8B"
"VSHL.S8 $dst.D,$src.D,$tmp.D\t! arithmetic right shift packed8B"
%}
ins_encode %{
bool quad = false;
__ vnegI($tmp$$FloatRegister, $shift$$FloatRegister,
MacroAssembler::VELEM_SIZE_8, quad);
__ vshlSI($dst$$FloatRegister, $tmp$$FloatRegister, $src$$FloatRegister,
MacroAssembler::VELEM_SIZE_8, quad);
%}
ins_pipe(ialu_reg_reg);
%}
instruct vsra16B_reg(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 16 && !n->as_ShiftV()->is_var_shift());
match(Set dst (RShiftVB src shift));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -11188,13 +11389,33 @@ instruct vsrl16B_reg(vecX dst, vecX src, vecX shift) %{
%}
%}
instruct vsrl8B_immI(vecD dst, vecD src, immI shift) %{
predicate(n->as_Vector()->length() == 8);
instruct vsra16B_reg_var(vecX dst, vecX src, vecX shift, vecX tmp) %{
predicate(n->as_Vector()->length() == 16 && n->as_ShiftV()->is_var_shift());
match(Set dst (RShiftVB src shift));
effect(TEMP tmp);
size(4*2);
ins_cost(DEFAULT_COST*2);
format %{
"VNEG.S8 $tmp.Q,$shift.Q\n\t! neg packed16B"
"VSHL.S8 $dst.Q,$src.Q,$tmp.Q\t! arithmetic right shift packed16B"
%}
ins_encode %{
bool quad = true;
__ vnegI($tmp$$FloatRegister, $shift$$FloatRegister,
MacroAssembler::VELEM_SIZE_8, quad);
__ vshlSI($dst$$FloatRegister, $tmp$$FloatRegister, $src$$FloatRegister,
MacroAssembler::VELEM_SIZE_8, quad);
%}
ins_pipe(ialu_reg_reg);
%}
instruct vsra8B_immI(vecD dst, vecD src, immI shift) %{
predicate(n->as_Vector()->length() == 8 && assert_not_var_shift(n));
match(Set dst (RShiftVB src (RShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
format %{
"VSHR.S8 $dst.D,$src.D,$shift\t! logical right shift packed8B"
"VSHR.S8 $dst.D,$src.D,$shift\t! arithmetic right shift packed8B"
%}
ins_encode %{
bool quad = false;
@ -11204,13 +11425,13 @@ instruct vsrl8B_immI(vecD dst, vecD src, immI shift) %{
ins_pipe( ialu_reg_reg ); // FIXME
%}
instruct vsrl16B_immI(vecX dst, vecX src, immI shift) %{
predicate(n->as_Vector()->length() == 16);
match(Set dst (RShiftVB src shift));
instruct vsra16B_immI(vecX dst, vecX src, immI shift) %{
predicate(n->as_Vector()->length() == 16 && assert_not_var_shift(n));
match(Set dst (RShiftVB src (RShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
format %{
"VSHR.S8 $dst.Q,$src.Q,$shift\t! logical right shift packed16B"
"VSHR.S8 $dst.Q,$src.Q,$shift\t! arithmetic right shift packed16B"
%}
ins_encode %{
bool quad = true;
@ -11222,7 +11443,7 @@ instruct vsrl16B_immI(vecX dst, vecX src, immI shift) %{
// Shorts vector arithmetic right shift
instruct vsra4S_reg(vecD dst, vecD src, vecD shift) %{
predicate(n->as_Vector()->length() == 4);
predicate(n->as_Vector()->length() == 4 && !n->as_ShiftV()->is_var_shift());
match(Set dst (RShiftVS src shift));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -11231,8 +11452,28 @@ instruct vsra4S_reg(vecD dst, vecD src, vecD shift) %{
%}
%}
instruct vsra4S_reg_var(vecD dst, vecD src, vecD shift, vecD tmp) %{
predicate(n->as_Vector()->length() == 4 && n->as_ShiftV()->is_var_shift());
match(Set dst (RShiftVS src shift));
effect(TEMP tmp);
size(4*2);
ins_cost(DEFAULT_COST*2);
format %{
"VNEG.S8 $tmp.D,$shift.D\n\t! neg packed8B"
"VSHL.S16 $dst.D,$src.D,$tmp.D\t! arithmetic right shift packed4S"
%}
ins_encode %{
bool quad = false;
__ vnegI($tmp$$FloatRegister, $shift$$FloatRegister,
MacroAssembler::VELEM_SIZE_8, quad);
__ vshlSI($dst$$FloatRegister, $tmp$$FloatRegister, $src$$FloatRegister,
MacroAssembler::VELEM_SIZE_16, quad);
%}
ins_pipe(ialu_reg_reg);
%}
instruct vsra8S_reg(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 8);
predicate(n->as_Vector()->length() == 8 && !n->as_ShiftV()->is_var_shift());
match(Set dst (RShiftVS src shift));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -11241,13 +11482,33 @@ instruct vsra8S_reg(vecX dst, vecX src, vecX shift) %{
%}
%}
instruct vsra4S_immI(vecD dst, vecD src, immI shift) %{
predicate(n->as_Vector()->length() == 4);
instruct vsra8S_reg_var(vecX dst, vecX src, vecX shift, vecX tmp) %{
predicate(n->as_Vector()->length() == 8 && n->as_ShiftV()->is_var_shift());
match(Set dst (RShiftVS src shift));
effect(TEMP tmp);
size(4*2);
ins_cost(DEFAULT_COST*2);
format %{
"VNEG.S8 $tmp.Q,$shift.Q\n\t! neg packed16B"
"VSHL.S16 $dst.Q,$src.Q,$tmp.Q\t! arithmetic right shift packed8S"
%}
ins_encode %{
bool quad = true;
__ vnegI($tmp$$FloatRegister, $shift$$FloatRegister,
MacroAssembler::VELEM_SIZE_8, quad);
__ vshlSI($dst$$FloatRegister, $tmp$$FloatRegister, $src$$FloatRegister,
MacroAssembler::VELEM_SIZE_16, quad);
%}
ins_pipe(ialu_reg_reg);
%}
instruct vsra4S_immI(vecD dst, vecD src, immI shift) %{
predicate(n->as_Vector()->length() == 4 && assert_not_var_shift(n));
match(Set dst (RShiftVS src (RShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
format %{
"VSHR.S16 $dst.D,$src.D,$shift\t! logical right shift packed4S"
"VSHR.S16 $dst.D,$src.D,$shift\t! arithmetic right shift packed4S"
%}
ins_encode %{
bool quad = false;
@ -11258,12 +11519,12 @@ instruct vsra4S_immI(vecD dst, vecD src, immI shift) %{
%}
instruct vsra8S_immI(vecX dst, vecX src, immI shift) %{
predicate(n->as_Vector()->length() == 8);
match(Set dst (RShiftVS src shift));
predicate(n->as_Vector()->length() == 8 && assert_not_var_shift(n));
match(Set dst (RShiftVS src (RShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
format %{
"VSHR.S16 $dst.Q,$src.Q,$shift\t! logical right shift packed8S"
"VSHR.S16 $dst.Q,$src.Q,$shift\t! arithmetic right shift packed8S"
%}
ins_encode %{
bool quad = true;
@ -11275,7 +11536,7 @@ instruct vsra8S_immI(vecX dst, vecX src, immI shift) %{
// Integers vector arithmetic right shift
instruct vsra2I_reg(vecD dst, vecD src, vecD shift) %{
predicate(n->as_Vector()->length() == 2);
predicate(n->as_Vector()->length() == 2 && !n->as_ShiftV()->is_var_shift());
match(Set dst (RShiftVI src shift));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -11284,8 +11545,28 @@ instruct vsra2I_reg(vecD dst, vecD src, vecD shift) %{
%}
%}
instruct vsra2I_reg_var(vecD dst, vecD src, vecD shift, vecD tmp) %{
predicate(n->as_Vector()->length() == 2 && n->as_ShiftV()->is_var_shift());
match(Set dst (RShiftVI src shift));
effect(TEMP tmp);
size(4*2);
ins_cost(DEFAULT_COST*2);
format %{
"VNEG.S8 $tmp.D,$shift.D\n\t! neg packed8B"
"VSHL.S32 $dst.D,$src.D,$tmp.D\t! arithmetic right shift packed2I"
%}
ins_encode %{
bool quad = false;
__ vnegI($tmp$$FloatRegister, $shift$$FloatRegister,
MacroAssembler::VELEM_SIZE_8, quad);
__ vshlSI($dst$$FloatRegister, $tmp$$FloatRegister, $src$$FloatRegister,
MacroAssembler::VELEM_SIZE_32, quad);
%}
ins_pipe(ialu_reg_reg);
%}
instruct vsra4I_reg(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 4);
predicate(n->as_Vector()->length() == 4 && !n->as_ShiftV()->is_var_shift());
match(Set dst (RShiftVI src shift));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -11294,13 +11575,33 @@ instruct vsra4I_reg(vecX dst, vecX src, vecX shift) %{
%}
%}
instruct vsra2I_immI(vecD dst, vecD src, immI shift) %{
predicate(n->as_Vector()->length() == 2);
instruct vsra4I_reg_var(vecX dst, vecX src, vecX shift, vecX tmp) %{
predicate(n->as_Vector()->length() == 4 && n->as_ShiftV()->is_var_shift());
match(Set dst (RShiftVI src shift));
effect(TEMP tmp);
size(4*2);
ins_cost(DEFAULT_COST*2);
format %{
"VNEG.S8 $tmp.Q,$shift.Q\n\t! neg packed16B"
"VSHL.S32 $dst.Q,$src.Q,$tmp.Q\t! arithmetic right shift packed4I"
%}
ins_encode %{
bool quad = true;
__ vnegI($tmp$$FloatRegister, $shift$$FloatRegister,
MacroAssembler::VELEM_SIZE_8, quad);
__ vshlSI($dst$$FloatRegister, $tmp$$FloatRegister, $src$$FloatRegister,
MacroAssembler::VELEM_SIZE_32, quad);
%}
ins_pipe(ialu_reg_reg);
%}
instruct vsra2I_immI(vecD dst, vecD src, immI shift) %{
predicate(n->as_Vector()->length() == 2 && assert_not_var_shift(n));
match(Set dst (RShiftVI src (RShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
format %{
"VSHR.S32 $dst.D,$src.D,$shift\t! logical right shift packed2I"
"VSHR.S32 $dst.D,$src.D,$shift\t! arithmetic right shift packed2I"
%}
ins_encode %{
bool quad = false;
@ -11311,12 +11612,12 @@ instruct vsra2I_immI(vecD dst, vecD src, immI shift) %{
%}
instruct vsra4I_immI(vecX dst, vecX src, immI shift) %{
predicate(n->as_Vector()->length() == 4);
match(Set dst (RShiftVI src shift));
predicate(n->as_Vector()->length() == 4 && assert_not_var_shift(n));
match(Set dst (RShiftVI src (RShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
format %{
"VSHR.S32 $dst.Q,$src.Q,$shift\t! logical right shift packed4I"
"VSHR.S32 $dst.Q,$src.Q,$shift\t! arithmetic right shift packed4I"
%}
ins_encode %{
bool quad = true;
@ -11328,7 +11629,7 @@ instruct vsra4I_immI(vecX dst, vecX src, immI shift) %{
// Longs vector arithmetic right shift
instruct vsra2L_reg(vecX dst, vecX src, vecX shift) %{
predicate(n->as_Vector()->length() == 2);
predicate(n->as_Vector()->length() == 2 && !n->as_ShiftV()->is_var_shift());
match(Set dst (RShiftVL src shift));
size(4);
ins_cost(DEFAULT_COST); // FIXME
@ -11337,13 +11638,33 @@ instruct vsra2L_reg(vecX dst, vecX src, vecX shift) %{
%}
%}
instruct vsra2L_immI(vecX dst, vecX src, immI shift) %{
predicate(n->as_Vector()->length() == 2);
instruct vsra2L_reg_var(vecX dst, vecX src, vecX shift, vecX tmp) %{
predicate(n->as_Vector()->length() == 2 && n->as_ShiftV()->is_var_shift());
match(Set dst (RShiftVL src shift));
effect(TEMP tmp);
size(4*2);
ins_cost(DEFAULT_COST*2);
format %{
"VNEG.S8 $tmp.Q,$shift.Q\n\t! neg packed16B"
"VSHL.S64 $dst.Q,$src.Q,$tmp.Q\t! arithmetic right shift packed2L"
%}
ins_encode %{
bool quad = true;
__ vnegI($tmp$$FloatRegister, $shift$$FloatRegister,
MacroAssembler::VELEM_SIZE_8, quad);
__ vshlSI($dst$$FloatRegister, $tmp$$FloatRegister, $src$$FloatRegister,
MacroAssembler::VELEM_SIZE_64, quad);
%}
ins_pipe(ialu_reg_reg);
%}
instruct vsra2L_immI(vecX dst, vecX src, immI shift) %{
predicate(n->as_Vector()->length() == 2 && assert_not_var_shift(n));
match(Set dst (RShiftVL src (RShiftCntV shift)));
size(4);
ins_cost(DEFAULT_COST); // FIXME
format %{
"VSHR.S64 $dst.Q,$src.Q,$shift\t! logical right shift packed2L"
"VSHR.S64 $dst.Q,$src.Q,$shift\t! arithmetic right shift packed2L"
%}
ins_encode %{
bool quad = true;

10
src/hotspot/cpu/x86/sharedRuntime_x86_32.cpp
View File

@ -1862,12 +1862,14 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
__ cmpptr(Address(rbp, lock_slot_rbp_offset), (int32_t)NULL_WORD);
__ jcc(Assembler::equal, done);
}
// Must save rax, if if it is live now because cmpxchg must use it
if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
save_native_result(masm, ret_type, stack_slots);
}
// Must save rax, if it is live now because cmpxchg must use it
if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
save_native_result(masm, ret_type, stack_slots);
}
if (!UseHeavyMonitors) {
// get old displaced header
__ movptr(rbx, Address(rbp, lock_slot_rbp_offset));

10
src/hotspot/cpu/x86/sharedRuntime_x86_64.cpp
View File

@ -2064,13 +2064,15 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
// Simple recursive lock?
__ cmpptr(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int32_t)NULL_WORD);
__ jcc(Assembler::equal, done);
}
// Must save rax if if it is live now because cmpxchg must use it
if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
save_native_result(masm, ret_type, stack_slots);
}
// Must save rax if it is live now because cmpxchg must use it
if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
save_native_result(masm, ret_type, stack_slots);
}
if (!UseHeavyMonitors) {
// get address of the stack lock
__ lea(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
// get old displaced header

4
src/hotspot/share/oops/method.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -1198,7 +1198,7 @@ void Method::unlink_method() {
void Method::link_method(const methodHandle& h_method, TRAPS) {
// If the code cache is full, we may reenter this function for the
// leftover methods that weren't linked.
if (_i2i_entry != NULL) {
if (adapter() != NULL) {
return;
}
assert( _code == NULL, "nothing compiled yet" );

9
src/hotspot/share/opto/vectornode.hpp
View File

@ -541,7 +541,8 @@ class SqrtVDNode : public VectorNode {
// Class ShiftV functionality. This covers the common behaviors for all kinds
// of vector shifts.
class ShiftVNode : public VectorNode {
bool _is_var_shift;
private:
bool _is_var_shift;
public:
ShiftVNode(Node* in1, Node* in2, const TypeVect* vt, bool is_var_shift) :
VectorNode(in1,in2,vt), _is_var_shift(is_var_shift) {
@ -549,8 +550,12 @@ class ShiftVNode : public VectorNode {
}
virtual Node* Identity(PhaseGVN* phase);
virtual int Opcode() const = 0;
virtual uint hash() const { return VectorNode::hash() + _is_var_shift; }
virtual bool cmp(const Node& n) const {
return VectorNode::cmp(n) && _is_var_shift == ((ShiftVNode&)n)._is_var_shift;
}
bool is_var_shift() { return _is_var_shift;}
virtual uint size_of() const { return sizeof(ShiftVNode); }
virtual uint size_of() const { return sizeof(ShiftVNode); }
};
//------------------------------LShiftVBNode-----------------------------------

23
src/jdk.javadoc/share/classes/jdk/javadoc/internal/doclets/toolkit/taglets/TagletManager.java
View File

@ -250,23 +250,22 @@ public class TagletManager {
* @param fileManager the file manager to load classes and resources
*/
public void addCustomTag(String classname, JavaFileManager fileManager) {
ClassLoader tagClassLoader = fileManager.getClassLoader(TAGLET_PATH);
if (configuration.workArounds.accessInternalAPI()) {
Module thisModule = getClass().getModule();
Module tagletLoaderUnnamedModule = tagClassLoader.getUnnamedModule();
List<String> pkgs = List.of(
"jdk.javadoc.doclet",
"jdk.javadoc.internal.doclets.toolkit",
"jdk.javadoc.internal.doclets.formats.html");
pkgs.forEach(p -> thisModule.addOpens(p, tagletLoaderUnnamedModule));
}
try {
ClassLoader tagClassLoader;
tagClassLoader = fileManager.getClassLoader(TAGLET_PATH);
if (configuration.workArounds.accessInternalAPI()) {
Module thisModule = getClass().getModule();
Module tagletLoaderUnnamedModule = tagClassLoader.getUnnamedModule();
List<String> pkgs = List.of(
"jdk.javadoc.doclet",
"jdk.javadoc.internal.doclets.toolkit",
"jdk.javadoc.internal.doclets.formats.html");
pkgs.forEach(p -> thisModule.addOpens(p, tagletLoaderUnnamedModule));
}
Class<? extends jdk.javadoc.doclet.Taglet> customTagClass =
tagClassLoader.loadClass(classname).asSubclass(jdk.javadoc.doclet.Taglet.class);
jdk.javadoc.doclet.Taglet instance = customTagClass.getConstructor().newInstance();
registerTaglet(instance);
} catch (ReflectiveOperationException exc) {
} catch (ReflectiveOperationException | ExceptionInInitializerError | ClassCastException exc) {
messages.error("doclet.Error_taglet_not_registered", exc.getClass().getName(),
classname);
}

57
test/hotspot/jtreg/compiler/codecache/OverflowCodeCacheTest.java
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -23,7 +23,7 @@
/*
* @test OverflowCodeCacheTest
* @bug 8059550
* @bug 8059550 8279356
* @summary testing of code cache segments overflow
* @library /test/lib
* @modules java.base/jdk.internal.misc
@ -33,11 +33,14 @@
* @run driver jdk.test.lib.helpers.ClassFileInstaller sun.hotspot.WhiteBox
* @run main/othervm -Xbootclasspath/a:. -XX:+UnlockDiagnosticVMOptions
* -XX:+WhiteBoxAPI -XX:CompileCommand=compileonly,null::*
* -XX:-SegmentedCodeCache
* compiler.codecache.OverflowCodeCacheTest
* -XX:-SegmentedCodeCache -Xmixed
* compiler.codecache.OverflowCodeCacheTest CompilationDisabled
* @run main/othervm -Xbootclasspath/a:. -XX:+UnlockDiagnosticVMOptions
* -XX:+WhiteBoxAPI -XX:CompileCommand=compileonly,null::*
* -XX:+SegmentedCodeCache
* -XX:+SegmentedCodeCache -Xmixed
* compiler.codecache.OverflowCodeCacheTest CompilationDisabled
* @run main/othervm -Xbootclasspath/a:. -XX:+UnlockDiagnosticVMOptions
* -XX:+WhiteBoxAPI -XX:-SegmentedCodeCache -Xmixed
* compiler.codecache.OverflowCodeCacheTest
*/
@ -49,13 +52,21 @@ import sun.hotspot.code.BlobType;
import sun.hotspot.code.CodeBlob;
import java.lang.management.MemoryPoolMXBean;
import java.lang.reflect.Method;
import java.util.ArrayList;
import java.util.EnumSet;
class Helper {
// Uncommon signature to prevent sharing and force creation of a new adapter
public void method(float a, float b, float c, Object o) { }
}
public class OverflowCodeCacheTest {
private static final WhiteBox WHITE_BOX = WhiteBox.getWhiteBox();
private static boolean COMPILATION_DISABLED = false;
public static void main(String[] args) {
COMPILATION_DISABLED = args.length > 0;
EnumSet<BlobType> blobTypes = BlobType.getAvailable();
for (BlobType type : blobTypes) {
new OverflowCodeCacheTest(type).test();
@ -74,6 +85,8 @@ public class OverflowCodeCacheTest {
System.out.println("allocating till possible...");
ArrayList<Long> blobs = new ArrayList<>();
int compilationActivityMode = -1;
// Lock compilation to be able to better control code cache space
WHITE_BOX.lockCompilation();
try {
long addr;
int size = (int) (getHeapSize() >> 7);
@ -88,15 +101,43 @@ public class OverflowCodeCacheTest {
}
}
/* now, remember compilationActivityMode to check it later, after freeing, since we
possibly have no free cache for futher work */
possibly have no free cache for further work */
compilationActivityMode = WHITE_BOX.getCompilationActivityMode();
// Use smallest allocation size to make sure all of the available space
// is filled up. Don't free these below to put some pressure on the sweeper.
while ((addr = WHITE_BOX.allocateCodeBlob(1, type.id)) != 0) { }
} finally {
try {
// Trigger creation of a new adapter for Helper::method
// which will fail because we are out of code cache space.
Helper helper = new Helper();
} catch (VirtualMachineError e) {
// Expected
}
// Free code cache space
for (Long blob : blobs) {
WHITE_BOX.freeCodeBlob(blob);
}
// Convert some nmethods to zombie and then free them to re-enable compilation
WHITE_BOX.unlockCompilation();
WHITE_BOX.forceNMethodSweep();
WHITE_BOX.forceNMethodSweep();
// Trigger compilation of Helper::method which will hit an assert because
// adapter creation failed above due to a lack of code cache space.
Helper helper = new Helper();
for (int i = 0; i < 100_000; i++) {
helper.method(0, 0, 0, null);
}
}
// Only check this if compilation is disabled, otherwise the sweeper might have
// freed enough nmethods to allow for re-enabling compilation.
if (COMPILATION_DISABLED) {
Asserts.assertNotEquals(compilationActivityMode, 1 /* run_compilation*/,
"Compilation must be disabled when CodeCache(CodeHeap) overflows");
}
Asserts.assertNotEquals(compilationActivityMode, 1 /* run_compilation*/,
"Compilation must be disabled when CodeCache(CodeHeap) overflows");
}
private long getHeapSize() {

7
test/hotspot/jtreg/compiler/loopopts/TestSkeletonPredicateNegation.java
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2021 THL A29 Limited, a Tencent company. All rights reserved.
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2021, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -24,7 +24,6 @@
/**
* @test
* @requires vm.compiler2.enabled
* @bug 8273277
* @summary Skeleton predicates sometimes need to be negated
* @run main compiler.loopopts.TestSkeletonPredicateNegation
@ -50,11 +49,11 @@ public class TestSkeletonPredicateNegation {
}
public void mainTest (String[] args){
long loa11[] = new long[1987];
long loa11[] = new long[19];
for (long lo14 : loa11) {
TestSkeletonPredicateNegation.in0 = -128;
for (int i18 = 0; i18 < 52; i18++) {
for (int i18 = 0; i18 < 13; i18++) {
try {
loa11[TestSkeletonPredicateNegation.in0] %= 2275269548L;
Math.ceil(1374905370.2785515599);

50
test/langtools/jdk/javadoc/doclet/testCustomTagletRegistration/ClassCastExceptionTaglet.java Normal file
View File

@ -0,0 +1,50 @@
/*
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*/
import java.util.EnumSet;
import java.util.List;
import java.util.Set;
import javax.lang.model.element.Element;
import com.sun.source.doctree.DocTree;
import jdk.javadoc.doclet.Taglet;
public class ClassCastExceptionTaglet /* does NOT implement jdk.javadoc.doclet.Taglet */ {
public Set<Taglet.Location> getAllowedLocations() {
return EnumSet.allOf(Taglet.Location.class);
}
public boolean isInlineTag() {
return false;
}
public String getName() {
return "ClassCastExceptionTaglet";
}
public String toString(List<? extends DocTree> tags, Element element) {
return "";
}
}

60
test/langtools/jdk/javadoc/doclet/testCustomTagletRegistration/ExceptionInInitializerErrorTaglet.java Normal file
View File

@ -0,0 +1,60 @@
/*
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*/
import java.util.EnumSet;
import java.util.List;
import java.util.Set;
import javax.lang.model.element.Element;
import com.sun.source.doctree.DocTree;
import jdk.javadoc.doclet.Taglet;
public class ExceptionInInitializerErrorTaglet implements Taglet {
static {
if (true) {
throw new RuntimeException();
}
}
@Override
public Set<Taglet.Location> getAllowedLocations() {
return EnumSet.allOf(Taglet.Location.class);
}
@Override
public boolean isInlineTag() {
return false;
}
@Override
public String getName() {
return "ExceptionInInitializerErrorTaglet";
}
@Override
public String toString(List<? extends DocTree> tags, Element element) {
return "";
}
}

54
test/langtools/jdk/javadoc/doclet/testCustomTagletRegistration/InstantiationExceptionTaglet.java Normal file
View File

@ -0,0 +1,54 @@
/*
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*/
import java.util.EnumSet;
import java.util.List;
import java.util.Set;
import javax.lang.model.element.Element;
import com.sun.source.doctree.DocTree;
import jdk.javadoc.doclet.Taglet;
public abstract class InstantiationExceptionTaglet implements Taglet {
@Override
public Set<Taglet.Location> getAllowedLocations() {
return EnumSet.allOf(Taglet.Location.class);
}
@Override
public boolean isInlineTag() {
return false;
}
@Override
public String getName() {
return "InstantiationExceptionTaglet";
}
@Override
public String toString(List<? extends DocTree> tags, Element element) {
return "";
}
}

58
test/langtools/jdk/javadoc/doclet/testCustomTagletRegistration/InvocationTargetExceptionTaglet.java Normal file
View File

@ -0,0 +1,58 @@
/*
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*/
import java.util.EnumSet;
import java.util.List;
import java.util.Set;
import javax.lang.model.element.Element;
import com.sun.source.doctree.DocTree;
import jdk.javadoc.doclet.Taglet;
public class InvocationTargetExceptionTaglet implements Taglet {
public InvocationTargetExceptionTaglet() {
throw new RuntimeException();
}
@Override
public Set<Location> getAllowedLocations() {
return EnumSet.allOf(Location.class);
}
@Override
public boolean isInlineTag() {
return false;
}
@Override
public String getName() {
return "InvocationTargetExceptionTaglet";
}
@Override
public String toString(List<? extends DocTree> tags, Element element) {
return "";
}
}

56
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/*
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*/
import java.util.EnumSet;
import java.util.List;
import java.util.Set;
import javax.lang.model.element.Element;
import com.sun.source.doctree.DocTree;
import jdk.javadoc.doclet.Taglet;
public class NoSuchMethodExceptionNoNullaryCtorTaglet implements Taglet {
public NoSuchMethodExceptionNoNullaryCtorTaglet(Object obj) {}
@Override
public Set<Location> getAllowedLocations() {
return EnumSet.allOf(Taglet.Location.class);
}
@Override
public boolean isInlineTag() {
return false;
}
@Override
public String getName() {
return "NoSuchMethodExceptionNoNullaryCtorTaglet";
}
@Override
public String toString(List<? extends DocTree> tags, Element element) {
return "";
}
}

56
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/*
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*/
import java.util.EnumSet;
import java.util.List;
import java.util.Set;
import javax.lang.model.element.Element;
import com.sun.source.doctree.DocTree;
import jdk.javadoc.doclet.Taglet;
public class NoSuchMethodExceptionPrivateCtorTaglet implements Taglet {
private NoSuchMethodExceptionPrivateCtorTaglet() {}
@Override
public Set<Taglet.Location> getAllowedLocations() {
return EnumSet.allOf(Taglet.Location.class);
}
@Override
public boolean isInlineTag() {
return false;
}
@Override
public String getName() {
return "NoSuchMethodExceptionPrivateCtorTaglet";
}
@Override
public String toString(List<? extends DocTree> tags, Element element) {
return "";
}
}

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/*
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*/
/*
* @test
* @bug 8206181
* @library ../../lib
* @modules jdk.javadoc/jdk.javadoc.internal.tool
* @build javadoc.tester.* *
* @run main TestRegistrationErrors
*/
import java.io.IOException;
import java.nio.file.Files;
import java.nio.file.Path;
import java.util.regex.Matcher;
import java.util.regex.Pattern;
import java.util.stream.Stream;
import javadoc.tester.JavadocTester;
public class TestRegistrationErrors extends JavadocTester {
public static void main(String... args) throws Exception {
TestRegistrationErrors tester = new TestRegistrationErrors();
tester.runTests();
}
@Test
public void test() throws Exception {
try (Stream<Path> tagletClasses = findTagletClasses()) {
tagletClasses.forEach(p -> {
String tagletName = getTagletName(p);
javadoc("-d", "out-" + tagletName, // a directory per taglet
"-tagletpath", System.getProperty("test.classes"),
"-taglet", tagletName,
testSrc("TestRegistrationErrors.java")); // specify this file
checkExit(Exit.ERROR);
new OutputChecker(Output.OUT).checkUnique(Pattern.compile("thrown while trying to register Taglet"));
checkNoCrashes();
});
}
}
private static Stream<Path> findTagletClasses() throws IOException {
var path = Path.of(System.getProperty("test.classes"));
return Files.find(path, Integer.MAX_VALUE,
(p, a) -> a.isRegularFile() && p.toString().endsWith("Taglet.class"));
}
private static String getTagletName(Path tagletClass) {
Path fileName = tagletClass.getFileName();
return fileName.toString().substring(0, fileName.toString().lastIndexOf('.'));
}
protected void checkNoCrashes() {
checking("check crashes");
Matcher matcher = Pattern.compile("\\s*at.*\\(.*\\.java:\\d+\\)")
.matcher(getOutput(Output.STDERR));
if (!matcher.find()) {
passed("");
} else {
failed("Looks like a stacktrace: " + matcher.group());
}
}
}