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@ -1709,6 +1709,20 @@ int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
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return idivq_offset;
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return idivq_offset;
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}
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}
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void MacroAssembler::membar(Membar_mask_bits order_constraint) {
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address prev = pc() - NativeMembar::instruction_size;
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if (prev == code()->last_membar()) {
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NativeMembar *bar = NativeMembar_at(prev);
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// We are merging two memory barrier instructions. On AArch64 we
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// can do this simply by ORing them together.
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bar->set_kind(bar->get_kind() | order_constraint);
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BLOCK_COMMENT("merged membar");
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} else {
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code()->set_last_membar(pc());
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dmb(Assembler::barrier(order_constraint));
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}
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}
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// MacroAssembler routines found actually to be needed
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// MacroAssembler routines found actually to be needed
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void MacroAssembler::push(Register src)
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void MacroAssembler::push(Register src)
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@ -152,6 +152,13 @@ class MacroAssembler: public Assembler {
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strw(scratch, a);
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strw(scratch, a);
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}
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}
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void bind(Label& L) {
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Assembler::bind(L);
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code()->clear_last_membar();
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}
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void membar(Membar_mask_bits order_constraint);
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// Frame creation and destruction shared between JITs.
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// Frame creation and destruction shared between JITs.
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void build_frame(int framesize);
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void build_frame(int framesize);
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void remove_frame(int framesize);
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void remove_frame(int framesize);
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@ -101,6 +101,12 @@ class NativeInstruction VALUE_OBJ_CLASS_SPEC {
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static bool maybe_cpool_ref(address instr) {
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static bool maybe_cpool_ref(address instr) {
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return is_adrp_at(instr) || is_ldr_literal_at(instr);
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return is_adrp_at(instr) || is_ldr_literal_at(instr);
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}
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}
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bool is_Membar() {
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unsigned int insn = uint_at(0);
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return Instruction_aarch64::extract(insn, 31, 12) == 0b11010101000000110011 &&
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Instruction_aarch64::extract(insn, 7, 0) == 0b10111111;
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}
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};
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};
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inline NativeInstruction* nativeInstruction_at(address address) {
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inline NativeInstruction* nativeInstruction_at(address address) {
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@ -487,4 +493,15 @@ inline NativeCallTrampolineStub* nativeCallTrampolineStub_at(address addr) {
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return (NativeCallTrampolineStub*)addr;
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return (NativeCallTrampolineStub*)addr;
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}
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}
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class NativeMembar : public NativeInstruction {
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public:
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unsigned int get_kind() { return Instruction_aarch64::extract(uint_at(0), 11, 8); }
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void set_kind(int order_kind) { Instruction_aarch64::patch(addr_at(0), 11, 8, order_kind); }
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};
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inline NativeMembar *NativeMembar_at(address addr) {
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assert(nativeInstruction_at(addr)->is_Membar(), "no membar found");
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return (NativeMembar*)addr;
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}
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#endif // CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP
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#endif // CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP
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@ -375,6 +375,8 @@ class CodeBuffer: public StackObj {
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OopRecorder _default_oop_recorder; // override with initialize_oop_recorder
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OopRecorder _default_oop_recorder; // override with initialize_oop_recorder
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Arena* _overflow_arena;
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Arena* _overflow_arena;
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address _last_membar; // used to merge consecutive memory barriers
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address _decode_begin; // start address for decode
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address _decode_begin; // start address for decode
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address decode_begin();
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address decode_begin();
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@ -388,6 +390,7 @@ class CodeBuffer: public StackObj {
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_decode_begin = NULL;
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_decode_begin = NULL;
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_overflow_arena = NULL;
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_overflow_arena = NULL;
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_code_strings = CodeStrings();
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_code_strings = CodeStrings();
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_last_membar = NULL;
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}
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}
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void initialize(address code_start, csize_t code_size) {
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void initialize(address code_start, csize_t code_size) {
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@ -577,6 +580,10 @@ class CodeBuffer: public StackObj {
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OopRecorder* oop_recorder() const { return _oop_recorder; }
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OopRecorder* oop_recorder() const { return _oop_recorder; }
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CodeStrings& strings() { return _code_strings; }
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CodeStrings& strings() { return _code_strings; }
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address last_membar() const { return _last_membar; }
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void set_last_membar(address a) { _last_membar = a; }
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void clear_last_membar() { set_last_membar(NULL); }
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void free_strings() {
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void free_strings() {
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if (!_code_strings.is_null()) {
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if (!_code_strings.is_null()) {
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_code_strings.free(); // sets _strings Null as a side-effect.
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_code_strings.free(); // sets _strings Null as a side-effect.
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