8187573: [s390] z/Architecture Vector Facility Support
Reviewed-by: mdoerr
This commit is contained in:
Lutz Schmidt
parent
070104325c
commit
6d015ba502
@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2016 SAP SE. All rights reserved.
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* Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2016, 2017 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -250,7 +250,6 @@ class Address VALUE_OBJ_CLASS_SPEC {
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bool is_RSform() { return has_base() && !has_index() && is_disp12(); }
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bool is_RSYform() { return has_base() && !has_index() && is_disp20(); }
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bool is_RXform() { return has_base() && has_index() && is_disp12(); }
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bool is_RXEform() { return has_base() && has_index() && is_disp12(); }
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bool is_RXYform() { return has_base() && has_index() && is_disp20(); }
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bool uses(Register r) { return _base == r || _index == r; };
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@ -1093,7 +1092,194 @@ class Assembler : public AbstractAssembler {
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#define TRTT_ZOPC (unsigned int)(0xb9 << 24 | 0x90 << 16)
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// Miscellaneous Operations
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//---------------------------
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//-- Vector Instructions --
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//---------------------------
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//---< Vector Support Instructions >---
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//--- Load (memory) ---
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#define VLM_ZOPC (unsigned long)(0xe7L << 40 | 0x36L << 0) // load full vreg range (n * 128 bit)
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#define VL_ZOPC (unsigned long)(0xe7L << 40 | 0x06L << 0) // load full vreg (128 bit)
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#define VLEB_ZOPC (unsigned long)(0xe7L << 40 | 0x00L << 0) // load vreg element (8 bit)
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#define VLEH_ZOPC (unsigned long)(0xe7L << 40 | 0x01L << 0) // load vreg element (16 bit)
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#define VLEF_ZOPC (unsigned long)(0xe7L << 40 | 0x03L << 0) // load vreg element (32 bit)
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#define VLEG_ZOPC (unsigned long)(0xe7L << 40 | 0x02L << 0) // load vreg element (64 bit)
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#define VLREP_ZOPC (unsigned long)(0xe7L << 40 | 0x05L << 0) // load and replicate into all vector elements
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#define VLLEZ_ZOPC (unsigned long)(0xe7L << 40 | 0x04L << 0) // load logical element and zero.
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// vector register gather
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#define VGEF_ZOPC (unsigned long)(0xe7L << 40 | 0x13L << 0) // gather element (32 bit), V1(M3) = [D2(V2(M3),B2)]
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#define VGEG_ZOPC (unsigned long)(0xe7L << 40 | 0x12L << 0) // gather element (64 bit), V1(M3) = [D2(V2(M3),B2)]
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// vector register scatter
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#define VSCEF_ZOPC (unsigned long)(0xe7L << 40 | 0x1bL << 0) // vector scatter element FW
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#define VSCEG_ZOPC (unsigned long)(0xe7L << 40 | 0x1aL << 0) // vector scatter element DW
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#define VLBB_ZOPC (unsigned long)(0xe7L << 40 | 0x07L << 0) // load vreg to block boundary (load to alignment).
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#define VLL_ZOPC (unsigned long)(0xe7L << 40 | 0x37L << 0) // load vreg with length.
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//--- Load (register) ---
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#define VLR_ZOPC (unsigned long)(0xe7L << 40 | 0x56L << 0) // copy full vreg (128 bit)
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#define VLGV_ZOPC (unsigned long)(0xe7L << 40 | 0x21L << 0) // copy vreg element -> GR
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#define VLVG_ZOPC (unsigned long)(0xe7L << 40 | 0x22L << 0) // copy GR -> vreg element
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#define VLVGP_ZOPC (unsigned long)(0xe7L << 40 | 0x62L << 0) // copy GR2, GR3 (disjoint pair) -> vreg
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// vector register pack: cut in half the size the source vector elements
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#define VPK_ZOPC (unsigned long)(0xe7L << 40 | 0x94L << 0) // just cut
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#define VPKS_ZOPC (unsigned long)(0xe7L << 40 | 0x97L << 0) // saturate as signed values
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#define VPKLS_ZOPC (unsigned long)(0xe7L << 40 | 0x95L << 0) // saturate as unsigned values
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// vector register unpack: double in size the source vector elements
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#define VUPH_ZOPC (unsigned long)(0xe7L << 40 | 0xd7L << 0) // signed, left half of the source vector elements
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#define VUPLH_ZOPC (unsigned long)(0xe7L << 40 | 0xd5L << 0) // unsigned, left half of the source vector elements
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#define VUPL_ZOPC (unsigned long)(0xe7L << 40 | 0xd6L << 0) // signed, right half of the source vector elements
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#define VUPLL_ZOPC (unsigned long)(0xe7L << 40 | 0xd4L << 0) // unsigned, right half of the source vector element
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// vector register merge
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#define VMRH_ZOPC (unsigned long)(0xe7L << 40 | 0x61L << 0) // register merge high (left half of source registers)
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#define VMRL_ZOPC (unsigned long)(0xe7L << 40 | 0x60L << 0) // register merge low (right half of source registers)
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// vector register permute
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#define VPERM_ZOPC (unsigned long)(0xe7L << 40 | 0x8cL << 0) // vector permute
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#define VPDI_ZOPC (unsigned long)(0xe7L << 40 | 0x84L << 0) // vector permute DW immediate
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// vector register replicate
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#define VREP_ZOPC (unsigned long)(0xe7L << 40 | 0x4dL << 0) // vector replicate
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#define VREPI_ZOPC (unsigned long)(0xe7L << 40 | 0x45L << 0) // vector replicate immediate
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#define VSEL_ZOPC (unsigned long)(0xe7L << 40 | 0x8dL << 0) // vector select
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#define VSEG_ZOPC (unsigned long)(0xe7L << 40 | 0x5fL << 0) // vector sign-extend to DW (rightmost element in each DW).
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//--- Load (immediate) ---
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#define VLEIB_ZOPC (unsigned long)(0xe7L << 40 | 0x40L << 0) // load vreg element (16 bit imm to 8 bit)
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#define VLEIH_ZOPC (unsigned long)(0xe7L << 40 | 0x41L << 0) // load vreg element (16 bit imm to 16 bit)
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#define VLEIF_ZOPC (unsigned long)(0xe7L << 40 | 0x43L << 0) // load vreg element (16 bit imm to 32 bit)
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#define VLEIG_ZOPC (unsigned long)(0xe7L << 40 | 0x42L << 0) // load vreg element (16 bit imm to 64 bit)
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//--- Store ---
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#define VSTM_ZOPC (unsigned long)(0xe7L << 40 | 0x3eL << 0) // store full vreg range (n * 128 bit)
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#define VST_ZOPC (unsigned long)(0xe7L << 40 | 0x0eL << 0) // store full vreg (128 bit)
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#define VSTEB_ZOPC (unsigned long)(0xe7L << 40 | 0x08L << 0) // store vreg element (8 bit)
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#define VSTEH_ZOPC (unsigned long)(0xe7L << 40 | 0x09L << 0) // store vreg element (16 bit)
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#define VSTEF_ZOPC (unsigned long)(0xe7L << 40 | 0x0bL << 0) // store vreg element (32 bit)
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#define VSTEG_ZOPC (unsigned long)(0xe7L << 40 | 0x0aL << 0) // store vreg element (64 bit)
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#define VSTL_ZOPC (unsigned long)(0xe7L << 40 | 0x3fL << 0) // store vreg with length.
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//--- Misc ---
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#define VGM_ZOPC (unsigned long)(0xe7L << 40 | 0x46L << 0) // generate bit mask, [start..end] = '1', else '0'
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#define VGBM_ZOPC (unsigned long)(0xe7L << 40 | 0x44L << 0) // generate byte mask, bits(imm16) -> bytes
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//---< Vector Arithmetic Instructions >---
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// Load
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#define VLC_ZOPC (unsigned long)(0xe7L << 40 | 0xdeL << 0) // V1 := -V2, element size = 2**m
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#define VLP_ZOPC (unsigned long)(0xe7L << 40 | 0xdfL << 0) // V1 := |V2|, element size = 2**m
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// ADD
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#define VA_ZOPC (unsigned long)(0xe7L << 40 | 0xf3L << 0) // V1 := V2 + V3, element size = 2**m
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#define VACC_ZOPC (unsigned long)(0xe7L << 40 | 0xf1L << 0) // V1 := carry(V2 + V3), element size = 2**m
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// SUB
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#define VS_ZOPC (unsigned long)(0xe7L << 40 | 0xf7L << 0) // V1 := V2 - V3, element size = 2**m
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#define VSCBI_ZOPC (unsigned long)(0xe7L << 40 | 0xf5L << 0) // V1 := borrow(V2 - V3), element size = 2**m
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// MUL
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#define VML_ZOPC (unsigned long)(0xe7L << 40 | 0xa2L << 0) // V1 := V2 * V3, element size = 2**m
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#define VMH_ZOPC (unsigned long)(0xe7L << 40 | 0xa3L << 0) // V1 := V2 * V3, element size = 2**m
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#define VMLH_ZOPC (unsigned long)(0xe7L << 40 | 0xa1L << 0) // V1 := V2 * V3, element size = 2**m, unsigned
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#define VME_ZOPC (unsigned long)(0xe7L << 40 | 0xa6L << 0) // V1 := V2 * V3, element size = 2**m
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#define VMLE_ZOPC (unsigned long)(0xe7L << 40 | 0xa4L << 0) // V1 := V2 * V3, element size = 2**m, unsigned
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#define VMO_ZOPC (unsigned long)(0xe7L << 40 | 0xa7L << 0) // V1 := V2 * V3, element size = 2**m
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#define VMLO_ZOPC (unsigned long)(0xe7L << 40 | 0xa5L << 0) // V1 := V2 * V3, element size = 2**m, unsigned
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// MUL & ADD
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#define VMAL_ZOPC (unsigned long)(0xe7L << 40 | 0xaaL << 0) // V1 := V2 * V3 + V4, element size = 2**m
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#define VMAH_ZOPC (unsigned long)(0xe7L << 40 | 0xabL << 0) // V1 := V2 * V3 + V4, element size = 2**m
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#define VMALH_ZOPC (unsigned long)(0xe7L << 40 | 0xa9L << 0) // V1 := V2 * V3 + V4, element size = 2**m, unsigned
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#define VMAE_ZOPC (unsigned long)(0xe7L << 40 | 0xaeL << 0) // V1 := V2 * V3 + V4, element size = 2**m
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#define VMALE_ZOPC (unsigned long)(0xe7L << 40 | 0xacL << 0) // V1 := V2 * V3 + V4, element size = 2**m, unsigned
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#define VMAO_ZOPC (unsigned long)(0xe7L << 40 | 0xafL << 0) // V1 := V2 * V3 + V4, element size = 2**m
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#define VMALO_ZOPC (unsigned long)(0xe7L << 40 | 0xadL << 0) // V1 := V2 * V3 + V4, element size = 2**m, unsigned
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// Vector SUM
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#define VSUM_ZOPC (unsigned long)(0xe7L << 40 | 0x64L << 0) // V1[j] := toFW(sum(V2[i]) + V3[j]), subelements: byte or HW
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#define VSUMG_ZOPC (unsigned long)(0xe7L << 40 | 0x65L << 0) // V1[j] := toDW(sum(V2[i]) + V3[j]), subelements: HW or FW
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#define VSUMQ_ZOPC (unsigned long)(0xe7L << 40 | 0x67L << 0) // V1[j] := toQW(sum(V2[i]) + V3[j]), subelements: FW or DW
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// Average
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#define VAVG_ZOPC (unsigned long)(0xe7L << 40 | 0xf2L << 0) // V1 := (V2+V3+1)/2, signed, element size = 2**m
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#define VAVGL_ZOPC (unsigned long)(0xe7L << 40 | 0xf0L << 0) // V1 := (V2+V3+1)/2, unsigned, element size = 2**m
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// VECTOR Galois Field Multiply Sum
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#define VGFM_ZOPC (unsigned long)(0xe7L << 40 | 0xb4L << 0)
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#define VGFMA_ZOPC (unsigned long)(0xe7L << 40 | 0xbcL << 0)
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//---< Vector Logical Instructions >---
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// AND
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#define VN_ZOPC (unsigned long)(0xe7L << 40 | 0x68L << 0) // V1 := V2 & V3, element size = 2**m
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#define VNC_ZOPC (unsigned long)(0xe7L << 40 | 0x69L << 0) // V1 := V2 & ~V3, element size = 2**m
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// XOR
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#define VX_ZOPC (unsigned long)(0xe7L << 40 | 0x6dL << 0) // V1 := V2 ^ V3, element size = 2**m
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// NOR
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#define VNO_ZOPC (unsigned long)(0xe7L << 40 | 0x6bL << 0) // V1 := !(V2 | V3), element size = 2**m
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// OR
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#define VO_ZOPC (unsigned long)(0xe7L << 40 | 0x6aL << 0) // V1 := V2 | V3, element size = 2**m
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// Comparison (element-wise)
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#define VCEQ_ZOPC (unsigned long)(0xe7L << 40 | 0xf8L << 0) // V1 := (V2 == V3) ? 0xffff : 0x0000, element size = 2**m
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#define VCH_ZOPC (unsigned long)(0xe7L << 40 | 0xfbL << 0) // V1 := (V2 > V3) ? 0xffff : 0x0000, element size = 2**m, signed
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#define VCHL_ZOPC (unsigned long)(0xe7L << 40 | 0xf9L << 0) // V1 := (V2 > V3) ? 0xffff : 0x0000, element size = 2**m, unsigned
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// Max/Min (element-wise)
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#define VMX_ZOPC (unsigned long)(0xe7L << 40 | 0xffL << 0) // V1 := (V2 > V3) ? V2 : V3, element size = 2**m, signed
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#define VMXL_ZOPC (unsigned long)(0xe7L << 40 | 0xfdL << 0) // V1 := (V2 > V3) ? V2 : V3, element size = 2**m, unsigned
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#define VMN_ZOPC (unsigned long)(0xe7L << 40 | 0xfeL << 0) // V1 := (V2 < V3) ? V2 : V3, element size = 2**m, signed
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#define VMNL_ZOPC (unsigned long)(0xe7L << 40 | 0xfcL << 0) // V1 := (V2 < V3) ? V2 : V3, element size = 2**m, unsigned
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// Leading/Trailing Zeros, population count
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#define VCLZ_ZOPC (unsigned long)(0xe7L << 40 | 0x53L << 0) // V1 := leadingzeros(V2), element size = 2**m
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#define VCTZ_ZOPC (unsigned long)(0xe7L << 40 | 0x52L << 0) // V1 := trailingzeros(V2), element size = 2**m
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#define VPOPCT_ZOPC (unsigned long)(0xe7L << 40 | 0x50L << 0) // V1 := popcount(V2), bytewise!!
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// Rotate/Shift
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#define VERLLV_ZOPC (unsigned long)(0xe7L << 40 | 0x73L << 0) // V1 := rotateleft(V2), rotate count in V3 element
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#define VERLL_ZOPC (unsigned long)(0xe7L << 40 | 0x33L << 0) // V1 := rotateleft(V3), rotate count from d2(b2).
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#define VERIM_ZOPC (unsigned long)(0xe7L << 40 | 0x72L << 0) // Rotate then insert under mask. Read Principles of Operation!!
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#define VESLV_ZOPC (unsigned long)(0xe7L << 40 | 0x70L << 0) // V1 := SLL(V2, V3), unsigned, element-wise
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#define VESL_ZOPC (unsigned long)(0xe7L << 40 | 0x30L << 0) // V1 := SLL(V3), unsigned, shift count from d2(b2).
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#define VESRAV_ZOPC (unsigned long)(0xe7L << 40 | 0x7AL << 0) // V1 := SRA(V2, V3), signed, element-wise
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#define VESRA_ZOPC (unsigned long)(0xe7L << 40 | 0x3AL << 0) // V1 := SRA(V3), signed, shift count from d2(b2).
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#define VESRLV_ZOPC (unsigned long)(0xe7L << 40 | 0x78L << 0) // V1 := SRL(V2, V3), unsigned, element-wise
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#define VESRL_ZOPC (unsigned long)(0xe7L << 40 | 0x38L << 0) // V1 := SRL(V3), unsigned, shift count from d2(b2).
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#define VSL_ZOPC (unsigned long)(0xe7L << 40 | 0x74L << 0) // V1 := SLL(V2), unsigned, bit-count
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#define VSLB_ZOPC (unsigned long)(0xe7L << 40 | 0x75L << 0) // V1 := SLL(V2), unsigned, byte-count
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#define VSLDB_ZOPC (unsigned long)(0xe7L << 40 | 0x77L << 0) // V1 := SLL((V2,V3)), unsigned, byte-count
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#define VSRA_ZOPC (unsigned long)(0xe7L << 40 | 0x7eL << 0) // V1 := SRA(V2), signed, bit-count
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#define VSRAB_ZOPC (unsigned long)(0xe7L << 40 | 0x7fL << 0) // V1 := SRA(V2), signed, byte-count
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#define VSRL_ZOPC (unsigned long)(0xe7L << 40 | 0x7cL << 0) // V1 := SRL(V2), unsigned, bit-count
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#define VSRLB_ZOPC (unsigned long)(0xe7L << 40 | 0x7dL << 0) // V1 := SRL(V2), unsigned, byte-count
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// Test under Mask
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#define VTM_ZOPC (unsigned long)(0xe7L << 40 | 0xd8L << 0) // Like TM, set CC according to state of selected bits.
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//--------------------------------
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//-- Miscellaneous Operations --
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//--------------------------------
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// Execute
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#define EX_ZOPC (unsigned int)(68L << 24)
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@ -1280,6 +1466,21 @@ class Assembler : public AbstractAssembler {
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to_minus_infinity = 7
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};
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// Vector Register Element Type.
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enum VRegElemType {
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VRET_BYTE = 0,
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VRET_HW = 1,
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VRET_FW = 2,
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VRET_DW = 3,
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VRET_QW = 4
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};
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// Vector Operation Condition Code Control.
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enum VOpCCC {
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VOP_CCIGN = 0, // ignore, don't set CC
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VOP_CCSET = 1 // set the CC
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};
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// Inverse condition code, i.e. determine "15 - cc" for a given condition code cc.
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static branch_condition inverse_condition(branch_condition cc);
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static branch_condition inverse_float_condition(branch_condition cc);
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@ -1376,6 +1577,60 @@ class Assembler : public AbstractAssembler {
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return r;
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}
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static int64_t rsmask_48( Address a) { assert(a.is_RSform(), "bad address format"); return rsmask_48( a.disp12(), a.base()); }
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static int64_t rxmask_48( Address a) { if (a.is_RXform()) { return rxmask_48( a.disp12(), a.index(), a.base()); }
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else if (a.is_RSform()) { return rsmask_48( a.disp12(), a.base()); }
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else { guarantee(false, "bad address format"); return 0; }
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}
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static int64_t rsymask_48(Address a) { assert(a.is_RSYform(), "bad address format"); return rsymask_48(a.disp20(), a.base()); }
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static int64_t rxymask_48(Address a) { if (a.is_RXYform()) { return rxymask_48( a.disp20(), a.index(), a.base()); }
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else if (a.is_RSYform()) { return rsymask_48( a.disp20(), a.base()); }
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else { guarantee(false, "bad address format"); return 0; }
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}
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static int64_t rsmask_48( int64_t d2, Register b2) { return uimm12(d2, 20, 48) | regz(b2, 16, 48); }
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static int64_t rxmask_48( int64_t d2, Register x2, Register b2) { return uimm12(d2, 20, 48) | reg(x2, 12, 48) | regz(b2, 16, 48); }
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static int64_t rsymask_48(int64_t d2, Register b2) { return simm20(d2) | regz(b2, 16, 48); }
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static int64_t rxymask_48(int64_t d2, Register x2, Register b2) { return simm20(d2) | reg(x2, 12, 48) | regz(b2, 16, 48); }
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// Address calculated from d12(vx,b) - vx is vector index register.
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static int64_t rvmask_48( int64_t d2, VectorRegister x2, Register b2) { return uimm12(d2, 20, 48) | vreg(x2, 12) | regz(b2, 16, 48); }
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static int64_t vreg_mask(VectorRegister v, int pos) {
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return vreg(v, pos) | v->RXB_mask(pos);
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}
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// Vector Element Size Control. 4-bit field which indicates the size of the vector elements.
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static int64_t vesc_mask(int64_t size, int min_size, int max_size, int pos) {
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// min_size - minimum element size. Not all instructions support element sizes beginning with "byte".
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// max_size - maximum element size. Not all instructions support element sizes up to "QW".
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assert((min_size <= size) && (size <= max_size), "element size control out of range");
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return uimm4(size, pos, 48);
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}
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|
||||
// Vector Element IndeX. 4-bit field which indexes the target vector element.
|
||||
static int64_t veix_mask(int64_t ix, int el_size, int pos) {
|
||||
// el_size - size of the vector element. This is a VRegElemType enum value.
|
||||
// ix - vector element index.
|
||||
int max_ix = -1;
|
||||
switch (el_size) {
|
||||
case VRET_BYTE: max_ix = 15; break;
|
||||
case VRET_HW: max_ix = 7; break;
|
||||
case VRET_FW: max_ix = 3; break;
|
||||
case VRET_DW: max_ix = 1; break;
|
||||
case VRET_QW: max_ix = 0; break;
|
||||
default: guarantee(false, "bad vector element size %d", el_size); break;
|
||||
}
|
||||
assert((0 <= ix) && (ix <= max_ix), "element size out of range (0 <= %ld <= %d)", ix, max_ix);
|
||||
return uimm4(ix, pos, 48);
|
||||
}
|
||||
|
||||
// Vector Operation Condition Code Control. 4-bit field, one bit of which indicates if the condition code is to be set by the operation.
|
||||
static int64_t vccc_mask(int64_t flag, int pos) {
|
||||
assert((flag == VOP_CCIGN) || (flag == VOP_CCSET), "VCCC flag value out of range");
|
||||
return uimm4(flag, pos, 48);
|
||||
}
|
||||
|
||||
public:
|
||||
|
||||
//--------------------------------------------------
|
||||
@ -1453,6 +1708,8 @@ class Assembler : public AbstractAssembler {
|
||||
static long imm24(int64_t i24, int s, int len) { return imm(i24, 24) << (len-s-24); }
|
||||
static long imm32(int64_t i32, int s, int len) { return imm(i32, 32) << (len-s-32); }
|
||||
|
||||
static long vreg(VectorRegister v, int pos) { const int len = 48; return u_field(v->encoding()&0x0f, (len-pos)-1, (len-pos)-4) | v->RXB_mask(pos); }
|
||||
|
||||
static long fregt(FloatRegister r, int s, int len) { return freg(r,s,len); }
|
||||
static long freg( FloatRegister r, int s, int len) { return u_field(r->encoding(), (len-s)-1, (len-s)-4); }
|
||||
|
||||
@ -2125,6 +2382,397 @@ class Assembler : public AbstractAssembler {
|
||||
inline void z_trtt(Register r1, Register r2, int64_t m3);
|
||||
|
||||
|
||||
//---------------------------
|
||||
//-- Vector Instructions --
|
||||
//---------------------------
|
||||
|
||||
//---< Vector Support Instructions >---
|
||||
|
||||
// Load (transfer from memory)
|
||||
inline void z_vlm( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_vl( VectorRegister v1, int64_t d2, Register x2, Register b2);
|
||||
inline void z_vleb( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
|
||||
inline void z_vleh( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
|
||||
inline void z_vlef( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
|
||||
inline void z_vleg( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
|
||||
|
||||
// Gather/Scatter
|
||||
inline void z_vgef( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3);
|
||||
inline void z_vgeg( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3);
|
||||
|
||||
inline void z_vscef( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3);
|
||||
inline void z_vsceg( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3);
|
||||
|
||||
// load and replicate
|
||||
inline void z_vlrep( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
|
||||
inline void z_vlrepb(VectorRegister v1, int64_t d2, Register x2, Register b2);
|
||||
inline void z_vlreph(VectorRegister v1, int64_t d2, Register x2, Register b2);
|
||||
inline void z_vlrepf(VectorRegister v1, int64_t d2, Register x2, Register b2);
|
||||
inline void z_vlrepg(VectorRegister v1, int64_t d2, Register x2, Register b2);
|
||||
|
||||
inline void z_vllez( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
|
||||
inline void z_vllezb(VectorRegister v1, int64_t d2, Register x2, Register b2);
|
||||
inline void z_vllezh(VectorRegister v1, int64_t d2, Register x2, Register b2);
|
||||
inline void z_vllezf(VectorRegister v1, int64_t d2, Register x2, Register b2);
|
||||
inline void z_vllezg(VectorRegister v1, int64_t d2, Register x2, Register b2);
|
||||
|
||||
inline void z_vlbb( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
|
||||
inline void z_vll( VectorRegister v1, Register r3, int64_t d2, Register b2);
|
||||
|
||||
// Load (register to register)
|
||||
inline void z_vlr( VectorRegister v1, VectorRegister v2);
|
||||
|
||||
inline void z_vlgv( Register r1, VectorRegister v3, int64_t d2, Register b2, int64_t m4);
|
||||
inline void z_vlgvb( Register r1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_vlgvh( Register r1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_vlgvf( Register r1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_vlgvg( Register r1, VectorRegister v3, int64_t d2, Register b2);
|
||||
|
||||
inline void z_vlvg( VectorRegister v1, Register r3, int64_t d2, Register b2, int64_t m4);
|
||||
inline void z_vlvgb( VectorRegister v1, Register r3, int64_t d2, Register b2);
|
||||
inline void z_vlvgh( VectorRegister v1, Register r3, int64_t d2, Register b2);
|
||||
inline void z_vlvgf( VectorRegister v1, Register r3, int64_t d2, Register b2);
|
||||
inline void z_vlvgg( VectorRegister v1, Register r3, int64_t d2, Register b2);
|
||||
|
||||
inline void z_vlvgp( VectorRegister v1, Register r2, Register r3);
|
||||
|
||||
// vector register pack
|
||||
inline void z_vpk( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vpkh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vpkf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vpkg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
|
||||
inline void z_vpks( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5);
|
||||
inline void z_vpksh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vpksf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vpksg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vpkshs(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vpksfs(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vpksgs(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
|
||||
inline void z_vpkls( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5);
|
||||
inline void z_vpklsh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vpklsf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vpklsg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vpklshs(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vpklsfs(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vpklsgs(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
|
||||
// vector register unpack (sign-extended)
|
||||
inline void z_vuph( VectorRegister v1, VectorRegister v2, int64_t m3);
|
||||
inline void z_vuphb( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vuphh( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vuphf( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vupl( VectorRegister v1, VectorRegister v2, int64_t m3);
|
||||
inline void z_vuplb( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vuplh( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vuplf( VectorRegister v1, VectorRegister v2);
|
||||
|
||||
// vector register unpack (zero-extended)
|
||||
inline void z_vuplh( VectorRegister v1, VectorRegister v2, int64_t m3);
|
||||
inline void z_vuplhb( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vuplhh( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vuplhf( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vupll( VectorRegister v1, VectorRegister v2, int64_t m3);
|
||||
inline void z_vupllb( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vupllh( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vupllf( VectorRegister v1, VectorRegister v2);
|
||||
|
||||
// vector register merge high/low
|
||||
inline void z_vmrh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vmrhb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmrhh(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmrhf(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmrhg(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
|
||||
inline void z_vmrl( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vmrlb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmrlh(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmrlf(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmrlg(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
|
||||
// vector register permute
|
||||
inline void z_vperm( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4);
|
||||
inline void z_vpdi( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
|
||||
// vector register replicate
|
||||
inline void z_vrep( VectorRegister v1, VectorRegister v3, int64_t imm2, int64_t m4);
|
||||
inline void z_vrepb( VectorRegister v1, VectorRegister v3, int64_t imm2);
|
||||
inline void z_vreph( VectorRegister v1, VectorRegister v3, int64_t imm2);
|
||||
inline void z_vrepf( VectorRegister v1, VectorRegister v3, int64_t imm2);
|
||||
inline void z_vrepg( VectorRegister v1, VectorRegister v3, int64_t imm2);
|
||||
inline void z_vrepi( VectorRegister v1, int64_t imm2, int64_t m3);
|
||||
inline void z_vrepib(VectorRegister v1, int64_t imm2);
|
||||
inline void z_vrepih(VectorRegister v1, int64_t imm2);
|
||||
inline void z_vrepif(VectorRegister v1, int64_t imm2);
|
||||
inline void z_vrepig(VectorRegister v1, int64_t imm2);
|
||||
|
||||
inline void z_vsel( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4);
|
||||
inline void z_vseg( VectorRegister v1, VectorRegister v2, int64_t imm3);
|
||||
|
||||
// Load (immediate)
|
||||
inline void z_vleib( VectorRegister v1, int64_t imm2, int64_t m3);
|
||||
inline void z_vleih( VectorRegister v1, int64_t imm2, int64_t m3);
|
||||
inline void z_vleif( VectorRegister v1, int64_t imm2, int64_t m3);
|
||||
inline void z_vleig( VectorRegister v1, int64_t imm2, int64_t m3);
|
||||
|
||||
// Store
|
||||
inline void z_vstm( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_vst( VectorRegister v1, int64_t d2, Register x2, Register b2);
|
||||
inline void z_vsteb( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
|
||||
inline void z_vsteh( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
|
||||
inline void z_vstef( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
|
||||
inline void z_vsteg( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
|
||||
inline void z_vstl( VectorRegister v1, Register r3, int64_t d2, Register b2);
|
||||
|
||||
// Misc
|
||||
inline void z_vgm( VectorRegister v1, int64_t imm2, int64_t imm3, int64_t m4);
|
||||
inline void z_vgmb( VectorRegister v1, int64_t imm2, int64_t imm3);
|
||||
inline void z_vgmh( VectorRegister v1, int64_t imm2, int64_t imm3);
|
||||
inline void z_vgmf( VectorRegister v1, int64_t imm2, int64_t imm3);
|
||||
inline void z_vgmg( VectorRegister v1, int64_t imm2, int64_t imm3);
|
||||
|
||||
inline void z_vgbm( VectorRegister v1, int64_t imm2);
|
||||
inline void z_vzero( VectorRegister v1); // preferred method to set vreg to all zeroes
|
||||
inline void z_vone( VectorRegister v1); // preferred method to set vreg to all ones
|
||||
|
||||
//---< Vector Arithmetic Instructions >---
|
||||
|
||||
// Load
|
||||
inline void z_vlc( VectorRegister v1, VectorRegister v2, int64_t m3);
|
||||
inline void z_vlcb( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vlch( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vlcf( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vlcg( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vlp( VectorRegister v1, VectorRegister v2, int64_t m3);
|
||||
inline void z_vlpb( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vlph( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vlpf( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vlpg( VectorRegister v1, VectorRegister v2);
|
||||
|
||||
// ADD
|
||||
inline void z_va( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vab( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vah( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vaf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vag( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vaq( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vacc( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vaccb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vacch( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vaccf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vaccg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vaccq( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
|
||||
// SUB
|
||||
inline void z_vs( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vsb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vsh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vsf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vsg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vsq( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vscbi( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vscbib( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vscbih( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vscbif( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vscbig( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vscbiq( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
|
||||
// MULTIPLY
|
||||
inline void z_vml( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vmh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vmlh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vme( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vmle( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vmo( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vmlo( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
|
||||
// MULTIPLY & ADD
|
||||
inline void z_vmal( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
|
||||
inline void z_vmah( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
|
||||
inline void z_vmalh( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
|
||||
inline void z_vmae( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
|
||||
inline void z_vmale( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
|
||||
inline void z_vmao( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
|
||||
inline void z_vmalo( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
|
||||
|
||||
// VECTOR SUM
|
||||
inline void z_vsum( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vsumb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vsumh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vsumg( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vsumgh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vsumgf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vsumq( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vsumqf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vsumqg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
|
||||
// Average
|
||||
inline void z_vavg( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vavgb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vavgh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vavgf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vavgg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vavgl( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vavglb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vavglh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vavglf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vavglg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
|
||||
// VECTOR Galois Field Multiply Sum
|
||||
inline void z_vgfm( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vgfmb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vgfmh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vgfmf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vgfmg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
// VECTOR Galois Field Multiply Sum and Accumulate
|
||||
inline void z_vgfma( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
|
||||
inline void z_vgfmab( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4);
|
||||
inline void z_vgfmah( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4);
|
||||
inline void z_vgfmaf( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4);
|
||||
inline void z_vgfmag( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4);
|
||||
|
||||
//---< Vector Logical Instructions >---
|
||||
|
||||
// AND
|
||||
inline void z_vn( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vnc( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
|
||||
// XOR
|
||||
inline void z_vx( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
|
||||
// NOR
|
||||
inline void z_vno( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
|
||||
// OR
|
||||
inline void z_vo( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
|
||||
// Comparison (element-wise)
|
||||
inline void z_vceq( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5);
|
||||
inline void z_vceqb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vceqh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vceqf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vceqg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vceqbs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vceqhs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vceqfs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vceqgs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vch( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5);
|
||||
inline void z_vchb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vchh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vchf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vchg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vchbs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vchhs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vchfs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vchgs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vchl( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5);
|
||||
inline void z_vchlb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vchlh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vchlf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vchlg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vchlbs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vchlhs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vchlfs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vchlgs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
|
||||
// Max/Min (element-wise)
|
||||
inline void z_vmx( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vmxb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmxh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmxf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmxg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmxl( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vmxlb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmxlh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmxlf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmxlg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmn( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vmnb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmnh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmnf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmng( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmnl( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vmnlb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmnlh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmnlf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vmnlg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
|
||||
// Leading/Trailing Zeros, population count
|
||||
inline void z_vclz( VectorRegister v1, VectorRegister v2, int64_t m3);
|
||||
inline void z_vclzb( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vclzh( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vclzf( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vclzg( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vctz( VectorRegister v1, VectorRegister v2, int64_t m3);
|
||||
inline void z_vctzb( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vctzh( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vctzf( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vctzg( VectorRegister v1, VectorRegister v2);
|
||||
inline void z_vpopct( VectorRegister v1, VectorRegister v2, int64_t m3);
|
||||
|
||||
// Rotate/Shift
|
||||
inline void z_verllv( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_verllvb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_verllvh(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_verllvf(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_verllvg(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_verll( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2, int64_t m4);
|
||||
inline void z_verllb( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_verllh( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_verllf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_verllg( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_verim( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4, int64_t m5);
|
||||
inline void z_verimb( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4);
|
||||
inline void z_verimh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4);
|
||||
inline void z_verimf( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4);
|
||||
inline void z_verimg( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4);
|
||||
|
||||
inline void z_veslv( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_veslvb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_veslvh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_veslvf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_veslvg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vesl( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2, int64_t m4);
|
||||
inline void z_veslb( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_veslh( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_veslf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_veslg( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
|
||||
inline void z_vesrav( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vesravb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vesravh(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vesravf(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vesravg(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vesra( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2, int64_t m4);
|
||||
inline void z_vesrab( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_vesrah( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_vesraf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_vesrag( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_vesrlv( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
|
||||
inline void z_vesrlvb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vesrlvh(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vesrlvf(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vesrlvg(VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vesrl( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2, int64_t m4);
|
||||
inline void z_vesrlb( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_vesrlh( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_vesrlf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
inline void z_vesrlg( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
|
||||
|
||||
inline void z_vsl( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vslb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vsldb( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4);
|
||||
|
||||
inline void z_vsra( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vsrab( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vsrl( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
inline void z_vsrlb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
|
||||
|
||||
// Test under Mask
|
||||
inline void z_vtm( VectorRegister v1, VectorRegister v2);
|
||||
|
||||
|
||||
// Floatingpoint instructions
|
||||
// ==========================
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2016 SAP SE. All rights reserved.
|
||||
* Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2016, 2017 SAP SE. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -702,6 +702,396 @@ inline void Assembler::z_cvd(Register r1, int64_t d2, Register x2, Register b2)
|
||||
inline void Assembler::z_cvdg(Register r1, int64_t d2, Register x2, Register b2) { emit_48( CVDG_ZOPC | regt(r1, 8, 48) | reg(x2, 12, 48) | reg(b2, 16, 48) | simm20(d2)); }
|
||||
|
||||
|
||||
//---------------------------
|
||||
//-- Vector Instructions --
|
||||
//---------------------------
|
||||
|
||||
//---< Vector Support Instructions >---
|
||||
|
||||
// Load (transfer from memory)
|
||||
inline void Assembler::z_vlm( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {emit_48(VLM_ZOPC | vreg(v1, 8) | vreg(v3, 12) | rsmask_48(d2, b2)); }
|
||||
inline void Assembler::z_vl( VectorRegister v1, int64_t d2, Register x2, Register b2) {emit_48(VL_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2)); }
|
||||
inline void Assembler::z_vleb( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3) {emit_48(VLEB_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | veix_mask(m3, VRET_BYTE, 32)); }
|
||||
inline void Assembler::z_vleh( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3) {emit_48(VLEH_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | veix_mask(m3, VRET_HW, 32)); }
|
||||
inline void Assembler::z_vlef( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3) {emit_48(VLEF_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | veix_mask(m3, VRET_FW, 32)); }
|
||||
inline void Assembler::z_vleg( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3) {emit_48(VLEG_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | veix_mask(m3, VRET_DW, 32)); }
|
||||
|
||||
// Gather/Scatter
|
||||
inline void Assembler::z_vgef( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3) {emit_48(VGEF_ZOPC | vreg(v1, 8) | rvmask_48(d2, vx2, b2) | veix_mask(m3, VRET_FW, 32)); }
|
||||
inline void Assembler::z_vgeg( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3) {emit_48(VGEG_ZOPC | vreg(v1, 8) | rvmask_48(d2, vx2, b2) | veix_mask(m3, VRET_DW, 32)); }
|
||||
|
||||
inline void Assembler::z_vscef( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3) {emit_48(VSCEF_ZOPC | vreg(v1, 8) | rvmask_48(d2, vx2, b2) | veix_mask(m3, VRET_FW, 32)); }
|
||||
inline void Assembler::z_vsceg( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3) {emit_48(VSCEG_ZOPC | vreg(v1, 8) | rvmask_48(d2, vx2, b2) | veix_mask(m3, VRET_DW, 32)); }
|
||||
|
||||
// load and replicate
|
||||
inline void Assembler::z_vlrep( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3) {emit_48(VLREP_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | vesc_mask(m3, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vlrepb( VectorRegister v1, int64_t d2, Register x2, Register b2) {z_vlrep(v1, d2, x2, b2, VRET_BYTE); }// load byte and replicate to all vector elements of type 'B'
|
||||
inline void Assembler::z_vlreph( VectorRegister v1, int64_t d2, Register x2, Register b2) {z_vlrep(v1, d2, x2, b2, VRET_HW); } // load HW and replicate to all vector elements of type 'H'
|
||||
inline void Assembler::z_vlrepf( VectorRegister v1, int64_t d2, Register x2, Register b2) {z_vlrep(v1, d2, x2, b2, VRET_FW); } // load FW and replicate to all vector elements of type 'F'
|
||||
inline void Assembler::z_vlrepg( VectorRegister v1, int64_t d2, Register x2, Register b2) {z_vlrep(v1, d2, x2, b2, VRET_DW); } // load DW and replicate to all vector elements of type 'G'
|
||||
|
||||
inline void Assembler::z_vllez( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3) {emit_48(VLLEZ_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | vesc_mask(m3, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vllezb( VectorRegister v1, int64_t d2, Register x2, Register b2) {z_vllez(v1, d2, x2, b2, VRET_BYTE); }// load logical byte into left DW of VR, zero all other bit positions.
|
||||
inline void Assembler::z_vllezh( VectorRegister v1, int64_t d2, Register x2, Register b2) {z_vllez(v1, d2, x2, b2, VRET_HW); } // load logical HW into left DW of VR, zero all other bit positions.
|
||||
inline void Assembler::z_vllezf( VectorRegister v1, int64_t d2, Register x2, Register b2) {z_vllez(v1, d2, x2, b2, VRET_FW); } // load logical FW into left DW of VR, zero all other bit positions.
|
||||
inline void Assembler::z_vllezg( VectorRegister v1, int64_t d2, Register x2, Register b2) {z_vllez(v1, d2, x2, b2, VRET_DW); } // load logical DW into left DW of VR, zero all other bit positions.
|
||||
|
||||
inline void Assembler::z_vlbb( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3) {emit_48(VLBB_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | uimm4(m3, 32, 48)); }
|
||||
inline void Assembler::z_vll( VectorRegister v1, Register r3, int64_t d2, Register b2) {emit_48(VLL_ZOPC | vreg(v1, 8) | reg(r3, 12, 48) | rsmask_48(d2, b2)); }
|
||||
|
||||
// Load (register to register)
|
||||
inline void Assembler::z_vlr ( VectorRegister v1, VectorRegister v2) {emit_48(VLR_ZOPC | vreg(v1, 8) | vreg(v2, 12)); }
|
||||
|
||||
inline void Assembler::z_vlgv( Register r1, VectorRegister v3, int64_t d2, Register b2, int64_t m4) {emit_48(VLGV_ZOPC | reg(r1, 8, 48) | vreg(v3, 12) | rsmask_48(d2, b2) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vlgvb( Register r1, VectorRegister v3, int64_t d2, Register b2) {z_vlgv(r1, v3, d2, b2, VRET_BYTE); } // load byte from VR element (index d2(b2)) into GR (logical)
|
||||
inline void Assembler::z_vlgvh( Register r1, VectorRegister v3, int64_t d2, Register b2) {z_vlgv(r1, v3, d2, b2, VRET_HW); } // load HW from VR element (index d2(b2)) into GR (logical)
|
||||
inline void Assembler::z_vlgvf( Register r1, VectorRegister v3, int64_t d2, Register b2) {z_vlgv(r1, v3, d2, b2, VRET_FW); } // load FW from VR element (index d2(b2)) into GR (logical)
|
||||
inline void Assembler::z_vlgvg( Register r1, VectorRegister v3, int64_t d2, Register b2) {z_vlgv(r1, v3, d2, b2, VRET_DW); } // load DW from VR element (index d2(b2)) into GR.
|
||||
|
||||
inline void Assembler::z_vlvg( VectorRegister v1, Register r3, int64_t d2, Register b2, int64_t m4) {emit_48(VLVG_ZOPC | vreg(v1, 8) | reg(r3, 12, 48) | rsmask_48(d2, b2) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vlvgb( VectorRegister v1, Register r3, int64_t d2, Register b2) {z_vlvg(v1, r3, d2, b2, VRET_BYTE); }
|
||||
inline void Assembler::z_vlvgh( VectorRegister v1, Register r3, int64_t d2, Register b2) {z_vlvg(v1, r3, d2, b2, VRET_HW); }
|
||||
inline void Assembler::z_vlvgf( VectorRegister v1, Register r3, int64_t d2, Register b2) {z_vlvg(v1, r3, d2, b2, VRET_FW); }
|
||||
inline void Assembler::z_vlvgg( VectorRegister v1, Register r3, int64_t d2, Register b2) {z_vlvg(v1, r3, d2, b2, VRET_DW); }
|
||||
|
||||
inline void Assembler::z_vlvgp( VectorRegister v1, Register r2, Register r3) {emit_48(VLVGP_ZOPC | vreg(v1, 8) | reg(r2, 12, 48) | reg(r3, 16, 48)); }
|
||||
|
||||
// vector register pack
|
||||
inline void Assembler::z_vpk( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VPK_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_HW, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vpkh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vpk(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vpkf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vpk(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vpkg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vpk(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
|
||||
inline void Assembler::z_vpks( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5) {emit_48(VPKS_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_HW, VRET_DW, 32) | vccc_mask(cc5, 24)); }
|
||||
inline void Assembler::z_vpksh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vpks(v1, v2, v3, VRET_HW, VOP_CCIGN); } // vector element type 'H', don't set CC
|
||||
inline void Assembler::z_vpksf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vpks(v1, v2, v3, VRET_FW, VOP_CCIGN); } // vector element type 'F', don't set CC
|
||||
inline void Assembler::z_vpksg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vpks(v1, v2, v3, VRET_DW, VOP_CCIGN); } // vector element type 'G', don't set CC
|
||||
inline void Assembler::z_vpkshs( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vpks(v1, v2, v3, VRET_HW, VOP_CCSET); } // vector element type 'H', set CC
|
||||
inline void Assembler::z_vpksfs( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vpks(v1, v2, v3, VRET_FW, VOP_CCSET); } // vector element type 'F', set CC
|
||||
inline void Assembler::z_vpksgs( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vpks(v1, v2, v3, VRET_DW, VOP_CCSET); } // vector element type 'G', set CC
|
||||
|
||||
inline void Assembler::z_vpkls( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5) {emit_48(VPKLS_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_HW, VRET_DW, 32) | vccc_mask(cc5, 24)); }
|
||||
inline void Assembler::z_vpklsh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vpkls(v1, v2, v3, VRET_HW, VOP_CCIGN); } // vector element type 'H', don't set CC
|
||||
inline void Assembler::z_vpklsf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vpkls(v1, v2, v3, VRET_FW, VOP_CCIGN); } // vector element type 'F', don't set CC
|
||||
inline void Assembler::z_vpklsg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vpkls(v1, v2, v3, VRET_DW, VOP_CCIGN); } // vector element type 'G', don't set CC
|
||||
inline void Assembler::z_vpklshs(VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vpkls(v1, v2, v3, VRET_HW, VOP_CCSET); } // vector element type 'H', set CC
|
||||
inline void Assembler::z_vpklsfs(VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vpkls(v1, v2, v3, VRET_FW, VOP_CCSET); } // vector element type 'F', set CC
|
||||
inline void Assembler::z_vpklsgs(VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vpkls(v1, v2, v3, VRET_DW, VOP_CCSET); } // vector element type 'G', set CC
|
||||
|
||||
// vector register unpack (sign-extended)
|
||||
inline void Assembler::z_vuph( VectorRegister v1, VectorRegister v2, int64_t m3) {emit_48(VUPH_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vesc_mask(m3, VRET_BYTE, VRET_FW, 32)); }
|
||||
inline void Assembler::z_vuphb( VectorRegister v1, VectorRegister v2) {z_vuph(v1, v2, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vuphh( VectorRegister v1, VectorRegister v2) {z_vuph(v1, v2, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vuphf( VectorRegister v1, VectorRegister v2) {z_vuph(v1, v2, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vupl( VectorRegister v1, VectorRegister v2, int64_t m3) {emit_48(VUPL_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vesc_mask(m3, VRET_BYTE, VRET_FW, 32)); }
|
||||
inline void Assembler::z_vuplb( VectorRegister v1, VectorRegister v2) {z_vupl(v1, v2, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vuplh( VectorRegister v1, VectorRegister v2) {z_vupl(v1, v2, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vuplf( VectorRegister v1, VectorRegister v2) {z_vupl(v1, v2, VRET_FW); } // vector element type 'F'
|
||||
|
||||
// vector register unpack (zero-extended)
|
||||
inline void Assembler::z_vuplh( VectorRegister v1, VectorRegister v2, int64_t m3) {emit_48(VUPLH_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vesc_mask(m3, VRET_BYTE, VRET_FW, 32)); }
|
||||
inline void Assembler::z_vuplhb( VectorRegister v1, VectorRegister v2) {z_vuplh(v1, v2, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vuplhh( VectorRegister v1, VectorRegister v2) {z_vuplh(v1, v2, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vuplhf( VectorRegister v1, VectorRegister v2) {z_vuplh(v1, v2, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vupll( VectorRegister v1, VectorRegister v2, int64_t m3) {emit_48(VUPLL_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vesc_mask(m3, VRET_BYTE, VRET_FW, 32)); }
|
||||
inline void Assembler::z_vupllb( VectorRegister v1, VectorRegister v2) {z_vupll(v1, v2, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vupllh( VectorRegister v1, VectorRegister v2) {z_vupll(v1, v2, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vupllf( VectorRegister v1, VectorRegister v2) {z_vupll(v1, v2, VRET_FW); } // vector element type 'F'
|
||||
|
||||
// vector register merge high/low
|
||||
inline void Assembler::z_vmrh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMRH_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vmrhb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmrh(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vmrhh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmrh(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vmrhf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmrh(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vmrhg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmrh(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
|
||||
inline void Assembler::z_vmrl( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMRL_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vmrlb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmrh(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vmrlh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmrh(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vmrlf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmrh(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vmrlg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmrh(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
|
||||
// vector register permute
|
||||
inline void Assembler::z_vperm( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4) {emit_48(VPERM_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vreg(v4, 32)); }
|
||||
inline void Assembler::z_vpdi( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VPDI_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | uimm4(m4, 32, 48)); }
|
||||
|
||||
// vector register replicate
|
||||
inline void Assembler::z_vrep( VectorRegister v1, VectorRegister v3, int64_t imm2, int64_t m4) {emit_48(VREP_ZOPC | vreg(v1, 8) | vreg(v3, 12) | simm16(imm2, 16, 48) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vrepb( VectorRegister v1, VectorRegister v3, int64_t imm2) {z_vrep(v1, v3, imm2, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vreph( VectorRegister v1, VectorRegister v3, int64_t imm2) {z_vrep(v1, v3, imm2, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vrepf( VectorRegister v1, VectorRegister v3, int64_t imm2) {z_vrep(v1, v3, imm2, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vrepg( VectorRegister v1, VectorRegister v3, int64_t imm2) {z_vrep(v1, v3, imm2, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_vrepi( VectorRegister v1, int64_t imm2, int64_t m3) {emit_48(VREPI_ZOPC | vreg(v1, 8) | simm16(imm2, 16, 48) | vesc_mask(m3, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vrepib( VectorRegister v1, int64_t imm2) {z_vrepi(v1, imm2, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vrepih( VectorRegister v1, int64_t imm2) {z_vrepi(v1, imm2, VRET_HW); } // vector element type 'B'
|
||||
inline void Assembler::z_vrepif( VectorRegister v1, int64_t imm2) {z_vrepi(v1, imm2, VRET_FW); } // vector element type 'B'
|
||||
inline void Assembler::z_vrepig( VectorRegister v1, int64_t imm2) {z_vrepi(v1, imm2, VRET_DW); } // vector element type 'B'
|
||||
|
||||
inline void Assembler::z_vsel( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4) {emit_48(VSEL_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vreg(v4, 32)); }
|
||||
inline void Assembler::z_vseg( VectorRegister v1, VectorRegister v2, int64_t m3) {emit_48(VSEG_ZOPC | vreg(v1, 8) | vreg(v2, 12) | uimm4(m3, 32, 48)); }
|
||||
|
||||
// Load (immediate)
|
||||
inline void Assembler::z_vleib( VectorRegister v1, int64_t imm2, int64_t m3) {emit_48(VLEIB_ZOPC | vreg(v1, 8) | simm16(imm2, 32, 48) | veix_mask(m3, VRET_BYTE, 32)); }
|
||||
inline void Assembler::z_vleih( VectorRegister v1, int64_t imm2, int64_t m3) {emit_48(VLEIH_ZOPC | vreg(v1, 8) | simm16(imm2, 32, 48) | veix_mask(m3, VRET_HW, 32)); }
|
||||
inline void Assembler::z_vleif( VectorRegister v1, int64_t imm2, int64_t m3) {emit_48(VLEIF_ZOPC | vreg(v1, 8) | simm16(imm2, 32, 48) | veix_mask(m3, VRET_FW, 32)); }
|
||||
inline void Assembler::z_vleig( VectorRegister v1, int64_t imm2, int64_t m3) {emit_48(VLEIG_ZOPC | vreg(v1, 8) | simm16(imm2, 32, 48) | veix_mask(m3, VRET_DW, 32)); }
|
||||
|
||||
// Store
|
||||
inline void Assembler::z_vstm( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {emit_48(VSTM_ZOPC | vreg(v1, 8) | vreg(v3, 12) | rsmask_48(d2, b2)); }
|
||||
inline void Assembler::z_vst( VectorRegister v1, int64_t d2, Register x2, Register b2) {emit_48(VST_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2)); }
|
||||
inline void Assembler::z_vsteb( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3) {emit_48(VSTEB_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | veix_mask(m3, VRET_BYTE, 32)); }
|
||||
inline void Assembler::z_vsteh( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3) {emit_48(VSTEH_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | veix_mask(m3, VRET_HW, 32)); }
|
||||
inline void Assembler::z_vstef( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3) {emit_48(VSTEF_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | veix_mask(m3, VRET_FW, 32)); }
|
||||
inline void Assembler::z_vsteg( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3) {emit_48(VSTEG_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | veix_mask(m3, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vstl( VectorRegister v1, Register r3, int64_t d2, Register b2) {emit_48(VSTL_ZOPC | vreg(v1, 8) | reg(r3, 12, 48) | rsmask_48(d2, b2)); }
|
||||
|
||||
// Misc
|
||||
inline void Assembler::z_vgm( VectorRegister v1, int64_t imm2, int64_t imm3, int64_t m4) {emit_48(VGM_ZOPC | vreg(v1, 8) | uimm8( imm2, 16, 48) | uimm8(imm3, 24, 48) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vgmb( VectorRegister v1, int64_t imm2, int64_t imm3) {z_vgm(v1, imm2, imm3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vgmh( VectorRegister v1, int64_t imm2, int64_t imm3) {z_vgm(v1, imm2, imm3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vgmf( VectorRegister v1, int64_t imm2, int64_t imm3) {z_vgm(v1, imm2, imm3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vgmg( VectorRegister v1, int64_t imm2, int64_t imm3) {z_vgm(v1, imm2, imm3, VRET_DW); } // vector element type 'G'
|
||||
|
||||
inline void Assembler::z_vgbm( VectorRegister v1, int64_t imm2) {emit_48(VGBM_ZOPC | vreg(v1, 8) | uimm16(imm2, 16, 48)); }
|
||||
inline void Assembler::z_vzero( VectorRegister v1) {z_vgbm(v1, 0); } // preferred method to set vreg to all zeroes
|
||||
inline void Assembler::z_vone( VectorRegister v1) {z_vgbm(v1, 0xffff); } // preferred method to set vreg to all ones
|
||||
|
||||
//---< Vector Arithmetic Instructions >---
|
||||
|
||||
// Load
|
||||
inline void Assembler::z_vlc( VectorRegister v1, VectorRegister v2, int64_t m3) {emit_48(VLC_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vesc_mask(m3, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vlcb( VectorRegister v1, VectorRegister v2) {z_vlc(v1, v2, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vlch( VectorRegister v1, VectorRegister v2) {z_vlc(v1, v2, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vlcf( VectorRegister v1, VectorRegister v2) {z_vlc(v1, v2, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vlcg( VectorRegister v1, VectorRegister v2) {z_vlc(v1, v2, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_vlp( VectorRegister v1, VectorRegister v2, int64_t m3) {emit_48(VLP_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vesc_mask(m3, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vlpb( VectorRegister v1, VectorRegister v2) {z_vlp(v1, v2, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vlph( VectorRegister v1, VectorRegister v2) {z_vlp(v1, v2, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vlpf( VectorRegister v1, VectorRegister v2) {z_vlp(v1, v2, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vlpg( VectorRegister v1, VectorRegister v2) {z_vlp(v1, v2, VRET_DW); } // vector element type 'G'
|
||||
|
||||
// ADD
|
||||
inline void Assembler::z_va( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VA_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_QW, 32)); }
|
||||
inline void Assembler::z_vab( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_va(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vah( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_va(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vaf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_va(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vag( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_va(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_vaq( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_va(v1, v2, v3, VRET_QW); } // vector element type 'Q'
|
||||
inline void Assembler::z_vacc( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VACC_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_QW, 32)); }
|
||||
inline void Assembler::z_vaccb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vacc(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vacch( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vacc(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vaccf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vacc(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vaccg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vacc(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_vaccq( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vacc(v1, v2, v3, VRET_QW); } // vector element type 'Q'
|
||||
|
||||
// SUB
|
||||
inline void Assembler::z_vs( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VS_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_QW, 32)); }
|
||||
inline void Assembler::z_vsb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vs(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vsh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vs(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vsf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vs(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vsg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vs(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_vsq( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vs(v1, v2, v3, VRET_QW); } // vector element type 'Q'
|
||||
inline void Assembler::z_vscbi( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VSCBI_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_QW, 32)); }
|
||||
inline void Assembler::z_vscbib( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vscbi(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vscbih( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vscbi(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vscbif( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vscbi(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vscbig( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vscbi(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_vscbiq( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vscbi(v1, v2, v3, VRET_QW); } // vector element type 'Q'
|
||||
|
||||
// MULTIPLY
|
||||
inline void Assembler::z_vml( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VML_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_FW, 32)); }
|
||||
inline void Assembler::z_vmh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMH_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_FW, 32)); }
|
||||
inline void Assembler::z_vmlh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMLH_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_FW, 32)); }
|
||||
inline void Assembler::z_vme( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VME_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_FW, 32)); }
|
||||
inline void Assembler::z_vmle( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMLE_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_FW, 32)); }
|
||||
inline void Assembler::z_vmo( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMO_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_FW, 32)); }
|
||||
inline void Assembler::z_vmlo( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMLO_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_FW, 32)); }
|
||||
|
||||
// MULTIPLY & ADD
|
||||
inline void Assembler::z_vmal( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5) {emit_48(VMAL_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vreg(v4, 32) | vesc_mask(m5, VRET_BYTE, VRET_FW, 20)); }
|
||||
inline void Assembler::z_vmah( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5) {emit_48(VMAH_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vreg(v4, 32) | vesc_mask(m5, VRET_BYTE, VRET_FW, 20)); }
|
||||
inline void Assembler::z_vmalh( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5) {emit_48(VMALH_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vreg(v4, 32) | vesc_mask(m5, VRET_BYTE, VRET_FW, 20)); }
|
||||
inline void Assembler::z_vmae( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5) {emit_48(VMAE_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vreg(v4, 32) | vesc_mask(m5, VRET_BYTE, VRET_FW, 20)); }
|
||||
inline void Assembler::z_vmale( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5) {emit_48(VMALE_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vreg(v4, 32) | vesc_mask(m5, VRET_BYTE, VRET_FW, 20)); }
|
||||
inline void Assembler::z_vmao( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5) {emit_48(VMAO_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vreg(v4, 32) | vesc_mask(m5, VRET_BYTE, VRET_FW, 20)); }
|
||||
inline void Assembler::z_vmalo( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5) {emit_48(VMALO_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vreg(v4, 32) | vesc_mask(m5, VRET_BYTE, VRET_FW, 20)); }
|
||||
|
||||
// VECTOR SUM
|
||||
inline void Assembler::z_vsum( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VSUM_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_HW, 32)); }
|
||||
inline void Assembler::z_vsumb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vsum(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vsumh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vsum(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vsumg( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VSUMG_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_HW, VRET_FW, 32)); }
|
||||
inline void Assembler::z_vsumgh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vsumg(v1, v2, v3, VRET_HW); } // vector element type 'B'
|
||||
inline void Assembler::z_vsumgf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vsumg(v1, v2, v3, VRET_FW); } // vector element type 'H'
|
||||
inline void Assembler::z_vsumq( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VSUMQ_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_FW, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vsumqf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vsumq(v1, v2, v3, VRET_FW); } // vector element type 'B'
|
||||
inline void Assembler::z_vsumqg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vsumq(v1, v2, v3, VRET_DW); } // vector element type 'H'
|
||||
|
||||
// Average
|
||||
inline void Assembler::z_vavg( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VAVG_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vavgb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vavg(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vavgh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vavg(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vavgf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vavg(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vavgg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vavg(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_vavgl( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VAVGL_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vavglb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vavgl(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vavglh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vavgl(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vavglf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vavgl(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vavglg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vavgl(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
|
||||
// VECTOR Galois Field Multiply Sum
|
||||
inline void Assembler::z_vgfm( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VGFM_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vgfmb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vgfm(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vgfmh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vgfm(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vgfmf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vgfm(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vgfmg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vgfm(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_vgfma( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5) {emit_48(VGFMA_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vreg(v3, 16) | vesc_mask(m5, VRET_BYTE, VRET_DW, 20)); }
|
||||
inline void Assembler::z_vgfmab( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4) {z_vgfma(v1, v2, v3, v4, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vgfmah( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4) {z_vgfma(v1, v2, v3, v4, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vgfmaf( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4) {z_vgfma(v1, v2, v3, v4, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vgfmag( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4) {z_vgfma(v1, v2, v3, v4, VRET_DW); } // vector element type 'G'
|
||||
|
||||
//---< Vector Logical Instructions >---
|
||||
|
||||
// AND
|
||||
inline void Assembler::z_vn( VectorRegister v1, VectorRegister v2, VectorRegister v3) {emit_48(VN_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16)); }
|
||||
inline void Assembler::z_vnc( VectorRegister v1, VectorRegister v2, VectorRegister v3) {emit_48(VNC_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16)); }
|
||||
|
||||
// XOR
|
||||
inline void Assembler::z_vx( VectorRegister v1, VectorRegister v2, VectorRegister v3) {emit_48(VX_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16)); }
|
||||
|
||||
// NOR
|
||||
inline void Assembler::z_vno( VectorRegister v1, VectorRegister v2, VectorRegister v3) {emit_48(VNO_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16)); }
|
||||
|
||||
// OR
|
||||
inline void Assembler::z_vo( VectorRegister v1, VectorRegister v2, VectorRegister v3) {emit_48(VO_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16)); }
|
||||
|
||||
// Comparison (element-wise)
|
||||
inline void Assembler::z_vceq( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5) {emit_48(VCEQ_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32) | vccc_mask(cc5, 24)); }
|
||||
inline void Assembler::z_vceqb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vceq(v1, v2, v3, VRET_BYTE, VOP_CCIGN); } // vector element type 'B', don't set CC
|
||||
inline void Assembler::z_vceqh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vceq(v1, v2, v3, VRET_HW, VOP_CCIGN); } // vector element type 'H', don't set CC
|
||||
inline void Assembler::z_vceqf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vceq(v1, v2, v3, VRET_FW, VOP_CCIGN); } // vector element type 'F', don't set CC
|
||||
inline void Assembler::z_vceqg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vceq(v1, v2, v3, VRET_DW, VOP_CCIGN); } // vector element type 'G', don't set CC
|
||||
inline void Assembler::z_vceqbs( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vceq(v1, v2, v3, VRET_BYTE, VOP_CCSET); } // vector element type 'B', don't set CC
|
||||
inline void Assembler::z_vceqhs( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vceq(v1, v2, v3, VRET_HW, VOP_CCSET); } // vector element type 'H', don't set CC
|
||||
inline void Assembler::z_vceqfs( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vceq(v1, v2, v3, VRET_FW, VOP_CCSET); } // vector element type 'F', don't set CC
|
||||
inline void Assembler::z_vceqgs( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vceq(v1, v2, v3, VRET_DW, VOP_CCSET); } // vector element type 'G', don't set CC
|
||||
inline void Assembler::z_vch( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5) {emit_48(VCH_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32) | vccc_mask(cc5, 24)); }
|
||||
inline void Assembler::z_vchb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vch(v1, v2, v3, VRET_BYTE, VOP_CCIGN); } // vector element type 'B', don't set CC
|
||||
inline void Assembler::z_vchh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vch(v1, v2, v3, VRET_HW, VOP_CCIGN); } // vector element type 'H', don't set CC
|
||||
inline void Assembler::z_vchf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vch(v1, v2, v3, VRET_FW, VOP_CCIGN); } // vector element type 'F', don't set CC
|
||||
inline void Assembler::z_vchg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vch(v1, v2, v3, VRET_DW, VOP_CCIGN); } // vector element type 'G', don't set CC
|
||||
inline void Assembler::z_vchbs( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vch(v1, v2, v3, VRET_BYTE, VOP_CCSET); } // vector element type 'B', don't set CC
|
||||
inline void Assembler::z_vchhs( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vch(v1, v2, v3, VRET_HW, VOP_CCSET); } // vector element type 'H', don't set CC
|
||||
inline void Assembler::z_vchfs( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vch(v1, v2, v3, VRET_FW, VOP_CCSET); } // vector element type 'F', don't set CC
|
||||
inline void Assembler::z_vchgs( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vch(v1, v2, v3, VRET_DW, VOP_CCSET); } // vector element type 'G', don't set CC
|
||||
inline void Assembler::z_vchl( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5) {emit_48(VCHL_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32) | vccc_mask(cc5, 24)); }
|
||||
inline void Assembler::z_vchlb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vchl(v1, v2, v3, VRET_BYTE, VOP_CCIGN); } // vector element type 'B', don't set CC
|
||||
inline void Assembler::z_vchlh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vchl(v1, v2, v3, VRET_HW, VOP_CCIGN); } // vector element type 'H', don't set CC
|
||||
inline void Assembler::z_vchlf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vchl(v1, v2, v3, VRET_FW, VOP_CCIGN); } // vector element type 'F', don't set CC
|
||||
inline void Assembler::z_vchlg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vchl(v1, v2, v3, VRET_DW, VOP_CCIGN); } // vector element type 'G', don't set CC
|
||||
inline void Assembler::z_vchlbs( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vchl(v1, v2, v3, VRET_BYTE, VOP_CCSET); } // vector element type 'B', don't set CC
|
||||
inline void Assembler::z_vchlhs( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vchl(v1, v2, v3, VRET_HW, VOP_CCSET); } // vector element type 'H', don't set CC
|
||||
inline void Assembler::z_vchlfs( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vchl(v1, v2, v3, VRET_FW, VOP_CCSET); } // vector element type 'F', don't set CC
|
||||
inline void Assembler::z_vchlgs( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vchl(v1, v2, v3, VRET_DW, VOP_CCSET); } // vector element type 'G', don't set CC
|
||||
|
||||
// Max/Min (element-wise)
|
||||
inline void Assembler::z_vmx( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMX_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vmxb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmx(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vmxh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmx(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vmxf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmx(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vmxg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmx(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_vmxl( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMXL_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vmxlb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmxl(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vmxlh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmxl(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vmxlf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmxl(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vmxlg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmxl(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_vmn( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMN_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vmnb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmn(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vmnh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmn(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vmnf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmn(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vmng( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmn(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_vmnl( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMNL_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vmnlb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmnl(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vmnlh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmnl(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vmnlf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmnl(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vmnlg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vmnl(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
|
||||
// Leading/Trailing Zeros, population count
|
||||
inline void Assembler::z_vclz( VectorRegister v1, VectorRegister v2, int64_t m3) {emit_48(VCLZ_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vesc_mask(m3, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vclzb( VectorRegister v1, VectorRegister v2) {z_vclz(v1, v2, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vclzh( VectorRegister v1, VectorRegister v2) {z_vclz(v1, v2, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vclzf( VectorRegister v1, VectorRegister v2) {z_vclz(v1, v2, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vclzg( VectorRegister v1, VectorRegister v2) {z_vclz(v1, v2, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_vctz( VectorRegister v1, VectorRegister v2, int64_t m3) {emit_48(VCTZ_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vesc_mask(m3, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vctzb( VectorRegister v1, VectorRegister v2) {z_vctz(v1, v2, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vctzh( VectorRegister v1, VectorRegister v2) {z_vctz(v1, v2, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vctzf( VectorRegister v1, VectorRegister v2) {z_vctz(v1, v2, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vctzg( VectorRegister v1, VectorRegister v2) {z_vctz(v1, v2, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_vpopct( VectorRegister v1, VectorRegister v2, int64_t m3) {emit_48(VPOPCT_ZOPC| vreg(v1, 8) | vreg(v2, 12) | vesc_mask(m3, VRET_BYTE, VRET_DW, 32)); }
|
||||
|
||||
// Rotate/Shift
|
||||
inline void Assembler::z_verllv( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VERLLV_ZOPC| vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_verllvb(VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_verllv(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_verllvh(VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_verllv(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_verllvf(VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_verllv(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_verllvg(VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_verllv(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_verll( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2, int64_t m4) {emit_48(VERLL_ZOPC | vreg(v1, 8) | vreg(v3, 12) | rsmask_48(d2, b2) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_verllb( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {z_verll(v1, v3, d2, b2, VRET_BYTE);}// vector element type 'B'
|
||||
inline void Assembler::z_verllh( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {z_verll(v1, v3, d2, b2, VRET_HW);} // vector element type 'H'
|
||||
inline void Assembler::z_verllf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {z_verll(v1, v3, d2, b2, VRET_FW);} // vector element type 'F'
|
||||
inline void Assembler::z_verllg( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {z_verll(v1, v3, d2, b2, VRET_DW);} // vector element type 'G'
|
||||
inline void Assembler::z_verim( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4, int64_t m5) {emit_48(VERLL_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | uimm8(imm4, 24, 48) | vesc_mask(m5, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_verimb( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4) {z_verim(v1, v2, v3, imm4, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_verimh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4) {z_verim(v1, v2, v3, imm4, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_verimf( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4) {z_verim(v1, v2, v3, imm4, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_verimg( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4) {z_verim(v1, v2, v3, imm4, VRET_DW); } // vector element type 'G'
|
||||
|
||||
inline void Assembler::z_veslv( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VESLV_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_veslvb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_veslv(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_veslvh( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_veslv(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_veslvf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_veslv(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_veslvg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_veslv(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_vesl( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2, int64_t m4) {emit_48(VESL_ZOPC | vreg(v1, 8) | vreg(v3, 12) | rsmask_48(d2, b2) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_veslb( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {z_vesl(v1, v3, d2, b2, VRET_BYTE);} // vector element type 'B'
|
||||
inline void Assembler::z_veslh( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {z_vesl(v1, v3, d2, b2, VRET_HW);} // vector element type 'H'
|
||||
inline void Assembler::z_veslf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {z_vesl(v1, v3, d2, b2, VRET_FW);} // vector element type 'F'
|
||||
inline void Assembler::z_veslg( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {z_vesl(v1, v3, d2, b2, VRET_DW);} // vector element type 'G'
|
||||
|
||||
inline void Assembler::z_vesrav( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VESRAV_ZOPC| vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vesravb(VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vesrav(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vesravh(VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vesrav(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vesravf(VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vesrav(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vesravg(VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vesrav(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_vesra( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2, int64_t m4) {emit_48(VESRA_ZOPC | vreg(v1, 8) | vreg(v3, 12) | rsmask_48(d2, b2) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vesrab( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {z_vesra(v1, v3, d2, b2, VRET_BYTE);}// vector element type 'B'
|
||||
inline void Assembler::z_vesrah( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {z_vesra(v1, v3, d2, b2, VRET_HW);} // vector element type 'H'
|
||||
inline void Assembler::z_vesraf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {z_vesra(v1, v3, d2, b2, VRET_FW);} // vector element type 'F'
|
||||
inline void Assembler::z_vesrag( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {z_vesra(v1, v3, d2, b2, VRET_DW);} // vector element type 'G'
|
||||
inline void Assembler::z_vesrlv( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VESRLV_ZOPC| vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vesrlvb(VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vesrlv(v1, v2, v3, VRET_BYTE); } // vector element type 'B'
|
||||
inline void Assembler::z_vesrlvh(VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vesrlv(v1, v2, v3, VRET_HW); } // vector element type 'H'
|
||||
inline void Assembler::z_vesrlvf(VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vesrlv(v1, v2, v3, VRET_FW); } // vector element type 'F'
|
||||
inline void Assembler::z_vesrlvg(VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vesrlv(v1, v2, v3, VRET_DW); } // vector element type 'G'
|
||||
inline void Assembler::z_vesrl( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2, int64_t m4) {emit_48(VESRL_ZOPC | vreg(v1, 8) | vreg(v3, 12) | rsmask_48(d2, b2) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
|
||||
inline void Assembler::z_vesrlb( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {z_vesrl(v1, v3, d2, b2, VRET_BYTE);}// vector element type 'B'
|
||||
inline void Assembler::z_vesrlh( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {z_vesrl(v1, v3, d2, b2, VRET_HW);} // vector element type 'H'
|
||||
inline void Assembler::z_vesrlf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {z_vesrl(v1, v3, d2, b2, VRET_FW);} // vector element type 'F'
|
||||
inline void Assembler::z_vesrlg( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2) {z_vesrl(v1, v3, d2, b2, VRET_DW);} // vector element type 'G'
|
||||
|
||||
inline void Assembler::z_vsl( VectorRegister v1, VectorRegister v2, VectorRegister v3) {emit_48(VSL_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16)); }
|
||||
inline void Assembler::z_vslb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {emit_48(VSLB_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16)); }
|
||||
inline void Assembler::z_vsldb( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4) {emit_48(VSLDB_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | uimm8(imm4, 24, 48)); }
|
||||
|
||||
inline void Assembler::z_vsra( VectorRegister v1, VectorRegister v2, VectorRegister v3) {emit_48(VSRA_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16)); }
|
||||
inline void Assembler::z_vsrab( VectorRegister v1, VectorRegister v2, VectorRegister v3) {emit_48(VSRAB_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16)); }
|
||||
inline void Assembler::z_vsrl( VectorRegister v1, VectorRegister v2, VectorRegister v3) {emit_48(VSRL_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16)); }
|
||||
inline void Assembler::z_vsrlb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {emit_48(VSRLB_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16)); }
|
||||
|
||||
// Test under Mask
|
||||
inline void Assembler::z_vtm( VectorRegister v1, VectorRegister v2) {emit_48(VTM_ZOPC | vreg(v1, 8) | vreg(v2, 12)); }
|
||||
|
||||
|
||||
//-------------------------------
|
||||
// FLOAT INSTRUCTIONS
|
||||
//-------------------------------
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2016 SAP SE. All rights reserved.
|
||||
* Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2016, 2017 SAP SE. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -35,3 +35,5 @@
|
||||
REGISTER_DEFINITION(Register, noreg);
|
||||
|
||||
REGISTER_DEFINITION(FloatRegister, fnoreg);
|
||||
|
||||
REGISTER_DEFINITION(VectorRegister, vnoreg);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2016 SAP SE. All rights reserved.
|
||||
* Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2016, 2017 SAP SE. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -46,3 +46,13 @@ const char* FloatRegisterImpl::name() const {
|
||||
};
|
||||
return is_valid() ? names[encoding()] : "fnoreg";
|
||||
}
|
||||
|
||||
const char* VectorRegisterImpl::name() const {
|
||||
const char* names[number_of_registers] = {
|
||||
"Z_V0", "Z_V1", "Z_V2", "Z_V3", "Z_V4", "Z_V5", "Z_V6", "Z_V7",
|
||||
"Z_V8", "Z_V9", "Z_V10", "Z_V11", "Z_V12", "Z_V13", "Z_V14", "Z_V15",
|
||||
"Z_V16", "Z_V17", "Z_V18", "Z_V19", "Z_V20", "Z_V21", "Z_V22", "Z_V23",
|
||||
"Z_V24", "Z_V25", "Z_V26", "Z_V27", "Z_V28", "Z_V29", "Z_V30", "Z_V31"
|
||||
};
|
||||
return is_valid() ? names[encoding()] : "fnoreg";
|
||||
}
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2016 SAP SE. All rights reserved.
|
||||
* Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2016, 2017 SAP SE. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -34,11 +34,6 @@ class VMRegImpl;
|
||||
|
||||
typedef VMRegImpl* VMReg;
|
||||
|
||||
// Use Register as shortcut.
|
||||
class RegisterImpl;
|
||||
typedef RegisterImpl* Register;
|
||||
|
||||
// The implementation of integer registers for z/Architecture.
|
||||
|
||||
// z/Architecture registers, see "LINUX for zSeries ELF ABI Supplement", IBM March 2001
|
||||
//
|
||||
@ -57,6 +52,17 @@ typedef RegisterImpl* Register;
|
||||
// f1,f3,f5,f7 General purpose (volatile)
|
||||
// f8-f15 General purpose (nonvolatile)
|
||||
|
||||
|
||||
//===========================
|
||||
//=== Integer Registers ===
|
||||
//===========================
|
||||
|
||||
// Use Register as shortcut.
|
||||
class RegisterImpl;
|
||||
typedef RegisterImpl* Register;
|
||||
|
||||
// The implementation of integer registers for z/Architecture.
|
||||
|
||||
inline Register as_Register(int encoding) {
|
||||
return (Register)(long)encoding;
|
||||
}
|
||||
@ -110,6 +116,11 @@ CONSTANT_REGISTER_DECLARATION(Register, Z_R13, (13));
|
||||
CONSTANT_REGISTER_DECLARATION(Register, Z_R14, (14));
|
||||
CONSTANT_REGISTER_DECLARATION(Register, Z_R15, (15));
|
||||
|
||||
|
||||
//=============================
|
||||
//=== Condition Registers ===
|
||||
//=============================
|
||||
|
||||
// Use ConditionRegister as shortcut
|
||||
class ConditionRegisterImpl;
|
||||
typedef ConditionRegisterImpl* ConditionRegister;
|
||||
@ -159,7 +170,7 @@ CONSTANT_REGISTER_DECLARATION(ConditionRegister, Z_CR, (0));
|
||||
// dangers of defines.
|
||||
// If a particular file has a problem with these defines then it's possible
|
||||
// to turn them off in that file by defining
|
||||
// DONT_USE_REGISTER_DEFINES. Register_definition_s390.cpp does that
|
||||
// DONT_USE_REGISTER_DEFINES. Register_definitions_s390.cpp does that
|
||||
// so that it's able to provide real definitions of these registers
|
||||
// for use in debuggers and such.
|
||||
|
||||
@ -186,6 +197,11 @@ CONSTANT_REGISTER_DECLARATION(ConditionRegister, Z_CR, (0));
|
||||
#define Z_CR ((ConditionRegister)(Z_CR_ConditionRegisterEnumValue))
|
||||
#endif // DONT_USE_REGISTER_DEFINES
|
||||
|
||||
|
||||
//=========================
|
||||
//=== Float Registers ===
|
||||
//=========================
|
||||
|
||||
// Use FloatRegister as shortcut
|
||||
class FloatRegisterImpl;
|
||||
typedef FloatRegisterImpl* FloatRegister;
|
||||
@ -263,22 +279,6 @@ CONSTANT_REGISTER_DECLARATION(FloatRegister, Z_F15, (15));
|
||||
#define Z_F15 ((FloatRegister)( Z_F15_FloatRegisterEnumValue))
|
||||
#endif // DONT_USE_REGISTER_DEFINES
|
||||
|
||||
// Need to know the total number of registers of all sorts for SharedInfo.
|
||||
// Define a class that exports it.
|
||||
|
||||
class ConcreteRegisterImpl : public AbstractRegisterImpl {
|
||||
public:
|
||||
enum {
|
||||
number_of_registers =
|
||||
(RegisterImpl::number_of_registers +
|
||||
FloatRegisterImpl::number_of_registers)
|
||||
* 2 // register halves
|
||||
+ 1 // condition code register
|
||||
};
|
||||
static const int max_gpr;
|
||||
static const int max_fpr;
|
||||
};
|
||||
|
||||
// Single, Double and Quad fp reg classes. These exist to map the ADLC
|
||||
// encoding for a floating point register, to the FloatRegister number
|
||||
// desired by the macroassembler. A FloatRegister is a number between
|
||||
@ -329,6 +329,161 @@ class QuadFloatRegisterImpl {
|
||||
};
|
||||
|
||||
|
||||
//==========================
|
||||
//=== Vector Registers ===
|
||||
//==========================
|
||||
|
||||
// Use VectorRegister as shortcut
|
||||
class VectorRegisterImpl;
|
||||
typedef VectorRegisterImpl* VectorRegister;
|
||||
|
||||
// The implementation of vector registers for z/Architecture.
|
||||
|
||||
inline VectorRegister as_VectorRegister(int encoding) {
|
||||
return (VectorRegister)(long)encoding;
|
||||
}
|
||||
|
||||
class VectorRegisterImpl: public AbstractRegisterImpl {
|
||||
public:
|
||||
enum {
|
||||
number_of_registers = 32,
|
||||
number_of_arg_registers = 0
|
||||
};
|
||||
|
||||
// construction
|
||||
inline friend VectorRegister as_VectorRegister(int encoding);
|
||||
|
||||
inline VMReg as_VMReg();
|
||||
|
||||
// accessors
|
||||
int encoding() const {
|
||||
assert(is_valid(), "invalid register"); return value();
|
||||
}
|
||||
|
||||
bool is_valid() const { return 0 <= value() && value() < number_of_registers; }
|
||||
bool is_volatile() const { return true; }
|
||||
bool is_nonvolatile() const { return false; }
|
||||
|
||||
// Register fields in z/Architecture instructions are 4 bits wide, restricting the
|
||||
// addressable register set size to 16.
|
||||
// The vector register set size is 32, requiring an extension, by one bit, of the
|
||||
// register encoding. This is accomplished by the introduction of a RXB field in the
|
||||
// instruction. RXB = Register eXtension Bits.
|
||||
// The RXB field contains the MSBs (most significant bit) of the vector register numbers
|
||||
// used for this instruction. Assignment of MSB in RBX is by bit position of the
|
||||
// register field in the instruction.
|
||||
// Example:
|
||||
// The register field starting at bit position 12 in the instruction is assigned RXB bit 0b0100.
|
||||
int64_t RXB_mask(int pos) {
|
||||
if (encoding() >= number_of_registers/2) {
|
||||
switch (pos) {
|
||||
case 8: return ((int64_t)0b1000) << 8; // actual bit pos: 36
|
||||
case 12: return ((int64_t)0b0100) << 8; // actual bit pos: 37
|
||||
case 16: return ((int64_t)0b0010) << 8; // actual bit pos: 38
|
||||
case 32: return ((int64_t)0b0001) << 8; // actual bit pos: 39
|
||||
default:
|
||||
ShouldNotReachHere();
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
const char* name() const;
|
||||
|
||||
VectorRegister successor() const { return as_VectorRegister(encoding() + 1); }
|
||||
};
|
||||
|
||||
// The Vector registers of z/Architecture.
|
||||
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, vnoreg, (-1));
|
||||
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V0, (0));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V1, (1));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V2, (2));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V3, (3));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V4, (4));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V5, (5));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V6, (6));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V7, (7));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V8, (8));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V9, (9));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V10, (10));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V11, (11));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V12, (12));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V13, (13));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V14, (14));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V15, (15));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V16, (16));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V17, (17));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V18, (18));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V19, (19));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V20, (20));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V21, (21));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V22, (22));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V23, (23));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V24, (24));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V25, (25));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V26, (26));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V27, (27));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V28, (28));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V29, (29));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V30, (30));
|
||||
CONSTANT_REGISTER_DECLARATION(VectorRegister, Z_V31, (31));
|
||||
|
||||
#ifndef DONT_USE_REGISTER_DEFINES
|
||||
#define vnoreg ((VectorRegister)(vnoreg_VectorRegisterEnumValue))
|
||||
#define Z_V0 ((VectorRegister)( Z_V0_VectorRegisterEnumValue))
|
||||
#define Z_V1 ((VectorRegister)( Z_V1_VectorRegisterEnumValue))
|
||||
#define Z_V2 ((VectorRegister)( Z_V2_VectorRegisterEnumValue))
|
||||
#define Z_V3 ((VectorRegister)( Z_V3_VectorRegisterEnumValue))
|
||||
#define Z_V4 ((VectorRegister)( Z_V4_VectorRegisterEnumValue))
|
||||
#define Z_V5 ((VectorRegister)( Z_V5_VectorRegisterEnumValue))
|
||||
#define Z_V6 ((VectorRegister)( Z_V6_VectorRegisterEnumValue))
|
||||
#define Z_V7 ((VectorRegister)( Z_V7_VectorRegisterEnumValue))
|
||||
#define Z_V8 ((VectorRegister)( Z_V8_VectorRegisterEnumValue))
|
||||
#define Z_V9 ((VectorRegister)( Z_V9_VectorRegisterEnumValue))
|
||||
#define Z_V10 ((VectorRegister)( Z_V10_VectorRegisterEnumValue))
|
||||
#define Z_V11 ((VectorRegister)( Z_V11_VectorRegisterEnumValue))
|
||||
#define Z_V12 ((VectorRegister)( Z_V12_VectorRegisterEnumValue))
|
||||
#define Z_V13 ((VectorRegister)( Z_V13_VectorRegisterEnumValue))
|
||||
#define Z_V14 ((VectorRegister)( Z_V14_VectorRegisterEnumValue))
|
||||
#define Z_V15 ((VectorRegister)( Z_V15_VectorRegisterEnumValue))
|
||||
#define Z_V16 ((VectorRegister)( Z_V16_VectorRegisterEnumValue))
|
||||
#define Z_V17 ((VectorRegister)( Z_V17_VectorRegisterEnumValue))
|
||||
#define Z_V18 ((VectorRegister)( Z_V18_VectorRegisterEnumValue))
|
||||
#define Z_V19 ((VectorRegister)( Z_V19_VectorRegisterEnumValue))
|
||||
#define Z_V20 ((VectorRegister)( Z_V20_VectorRegisterEnumValue))
|
||||
#define Z_V21 ((VectorRegister)( Z_V21_VectorRegisterEnumValue))
|
||||
#define Z_V22 ((VectorRegister)( Z_V22_VectorRegisterEnumValue))
|
||||
#define Z_V23 ((VectorRegister)( Z_V23_VectorRegisterEnumValue))
|
||||
#define Z_V24 ((VectorRegister)( Z_V24_VectorRegisterEnumValue))
|
||||
#define Z_V25 ((VectorRegister)( Z_V25_VectorRegisterEnumValue))
|
||||
#define Z_V26 ((VectorRegister)( Z_V26_VectorRegisterEnumValue))
|
||||
#define Z_V27 ((VectorRegister)( Z_V27_VectorRegisterEnumValue))
|
||||
#define Z_V28 ((VectorRegister)( Z_V28_VectorRegisterEnumValue))
|
||||
#define Z_V29 ((VectorRegister)( Z_V29_VectorRegisterEnumValue))
|
||||
#define Z_V30 ((VectorRegister)( Z_V30_VectorRegisterEnumValue))
|
||||
#define Z_V31 ((VectorRegister)( Z_V31_VectorRegisterEnumValue))
|
||||
#endif // DONT_USE_REGISTER_DEFINES
|
||||
|
||||
|
||||
// Need to know the total number of registers of all sorts for SharedInfo.
|
||||
// Define a class that exports it.
|
||||
|
||||
class ConcreteRegisterImpl : public AbstractRegisterImpl {
|
||||
public:
|
||||
enum {
|
||||
number_of_registers =
|
||||
(RegisterImpl::number_of_registers +
|
||||
FloatRegisterImpl::number_of_registers)
|
||||
* 2 // register halves
|
||||
+ 1 // condition code register
|
||||
};
|
||||
static const int max_gpr;
|
||||
static const int max_fpr;
|
||||
};
|
||||
|
||||
|
||||
// Common register declarations used in assembler code.
|
||||
REGISTER_DECLARATION(Register, Z_EXC_OOP, Z_R2);
|
||||
REGISTER_DECLARATION(Register, Z_EXC_PC, Z_R3);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user