8322768: Optimize non-subword vector compress and expand APIs for AVX2 target.
Reviewed-by: epeter, sviswanathan
This commit is contained in:
Jatin Bhateja
parent
9d1a6d1484
commit
6d36eb78ad
@ -1,5 +1,5 @@
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/*
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* Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -816,8 +816,8 @@ private:
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void check_relocation(RelocationHolder const& rspec, int format);
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#endif
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void emit_data(jint data, relocInfo::relocType rtype, int format);
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void emit_data(jint data, RelocationHolder const& rspec, int format);
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void emit_data(jint data, relocInfo::relocType rtype, int format = 0);
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void emit_data(jint data, RelocationHolder const& rspec, int format = 0);
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void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
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void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
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@ -5282,6 +5282,42 @@ void C2_MacroAssembler::vector_mask_compress(KRegister dst, KRegister src, Regis
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kmov(dst, rtmp2);
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}
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#ifdef _LP64
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void C2_MacroAssembler::vector_compress_expand_avx2(int opcode, XMMRegister dst, XMMRegister src,
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XMMRegister mask, Register rtmp, Register rscratch,
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XMMRegister permv, XMMRegister xtmp, BasicType bt,
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int vec_enc) {
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assert(type2aelembytes(bt) >= 4, "");
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assert(opcode == Op_CompressV || opcode == Op_ExpandV, "");
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address compress_perm_table = nullptr;
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address expand_perm_table = nullptr;
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if (type2aelembytes(bt) == 8) {
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compress_perm_table = StubRoutines::x86::compress_perm_table64();
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expand_perm_table = StubRoutines::x86::expand_perm_table64();
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vmovmskpd(rtmp, mask, vec_enc);
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} else {
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compress_perm_table = StubRoutines::x86::compress_perm_table32();
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expand_perm_table = StubRoutines::x86::expand_perm_table32();
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vmovmskps(rtmp, mask, vec_enc);
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}
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shlq(rtmp, 5); // for 32 byte permute row.
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if (opcode == Op_CompressV) {
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lea(rscratch, ExternalAddress(compress_perm_table));
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} else {
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lea(rscratch, ExternalAddress(expand_perm_table));
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}
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addptr(rtmp, rscratch);
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vmovdqu(permv, Address(rtmp));
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vpermps(dst, permv, src, Assembler::AVX_256bit);
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vpxor(xtmp, xtmp, xtmp, vec_enc);
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// Blend the result with zero vector using permute mask, each column entry
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// in a permute table row contains either a valid permute index or a -1 (default)
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// value, this can potentially be used as a blending mask after
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// compressing/expanding the source vector lanes.
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vblendvps(dst, dst, xtmp, permv, vec_enc, false, permv);
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}
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#endif
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void C2_MacroAssembler::vector_compress_expand(int opcode, XMMRegister dst, XMMRegister src, KRegister mask,
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bool merge, BasicType bt, int vec_enc) {
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if (opcode == Op_CompressV) {
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2020, 2023, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2020, 2024, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -390,6 +390,10 @@ public:
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void vector_round_float_avx(XMMRegister dst, XMMRegister src, AddressLiteral float_sign_flip, AddressLiteral new_mxcsr, int vec_enc,
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Register tmp, XMMRegister xtmp1, XMMRegister xtmp2, XMMRegister xtmp3, XMMRegister xtmp4);
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void vector_compress_expand_avx2(int opcode, XMMRegister dst, XMMRegister src, XMMRegister mask,
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Register rtmp, Register rscratch, XMMRegister permv, XMMRegister xtmp,
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BasicType bt, int vec_enc);
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#endif // _LP64
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void udivI(Register rax, Register divisor, Register rdx);
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@ -951,6 +951,92 @@ address StubGenerator::generate_fp_mask(const char *stub_name, int64_t mask) {
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return start;
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}
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address StubGenerator::generate_compress_perm_table(const char *stub_name, int32_t esize) {
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__ align(CodeEntryAlignment);
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StubCodeMark mark(this, "StubRoutines", stub_name);
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address start = __ pc();
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if (esize == 32) {
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// Loop to generate 256 x 8 int compression permute index table. A row is
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// accessed using 8 bit index computed using vector mask. An entry in
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// a row holds either a valid permute index corresponding to set bit position
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// or a -1 (default) value.
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for (int mask = 0; mask < 256; mask++) {
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int ctr = 0;
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for (int j = 0; j < 8; j++) {
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if (mask & (1 << j)) {
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__ emit_data(j, relocInfo::none);
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ctr++;
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}
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}
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for (; ctr < 8; ctr++) {
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__ emit_data(-1, relocInfo::none);
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}
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}
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} else {
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assert(esize == 64, "");
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// Loop to generate 16 x 4 long compression permute index table. A row is
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// accessed using 4 bit index computed using vector mask. An entry in
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// a row holds either a valid permute index pair for a quadword corresponding
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// to set bit position or a -1 (default) value.
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for (int mask = 0; mask < 16; mask++) {
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int ctr = 0;
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for (int j = 0; j < 4; j++) {
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if (mask & (1 << j)) {
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__ emit_data(2 * j, relocInfo::none);
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__ emit_data(2 * j + 1, relocInfo::none);
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ctr++;
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}
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}
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for (; ctr < 4; ctr++) {
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__ emit_data64(-1L, relocInfo::none);
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}
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}
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}
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return start;
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}
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address StubGenerator::generate_expand_perm_table(const char *stub_name, int32_t esize) {
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__ align(CodeEntryAlignment);
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StubCodeMark mark(this, "StubRoutines", stub_name);
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address start = __ pc();
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if (esize == 32) {
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// Loop to generate 256 x 8 int expand permute index table. A row is accessed
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// using 8 bit index computed using vector mask. An entry in a row holds either
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// a valid permute index (starting from least significant lane) placed at poisition
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// corresponding to set bit position or a -1 (default) value.
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for (int mask = 0; mask < 256; mask++) {
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int ctr = 0;
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for (int j = 0; j < 8; j++) {
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if (mask & (1 << j)) {
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__ emit_data(ctr++, relocInfo::none);
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} else {
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__ emit_data(-1, relocInfo::none);
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}
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}
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}
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} else {
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assert(esize == 64, "");
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// Loop to generate 16 x 4 long expand permute index table. A row is accessed
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// using 4 bit index computed using vector mask. An entry in a row holds either
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// a valid doubleword permute index pair representing a quadword index (starting
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// from least significant lane) placed at poisition corresponding to set bit
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// position or a -1 (default) value.
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for (int mask = 0; mask < 16; mask++) {
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int ctr = 0;
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for (int j = 0; j < 4; j++) {
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if (mask & (1 << j)) {
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__ emit_data(2 * ctr, relocInfo::none);
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__ emit_data(2 * ctr + 1, relocInfo::none);
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ctr++;
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} else {
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__ emit_data64(-1L, relocInfo::none);
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}
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}
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}
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}
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return start;
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}
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address StubGenerator::generate_vector_mask(const char *stub_name, int64_t mask) {
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__ align(CodeEntryAlignment);
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StubCodeMark mark(this, "StubRoutines", stub_name);
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@ -4095,6 +4181,13 @@ void StubGenerator::generate_compiler_stubs() {
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StubRoutines::x86::_vector_reverse_byte_perm_mask_int = generate_vector_reverse_byte_perm_mask_int("perm_mask_int");
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StubRoutines::x86::_vector_reverse_byte_perm_mask_short = generate_vector_reverse_byte_perm_mask_short("perm_mask_short");
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if (VM_Version::supports_avx2() && !VM_Version::supports_avx512vl()) {
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StubRoutines::x86::_compress_perm_table32 = generate_compress_perm_table("compress_perm_table32", 32);
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StubRoutines::x86::_compress_perm_table64 = generate_compress_perm_table("compress_perm_table64", 64);
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StubRoutines::x86::_expand_perm_table32 = generate_expand_perm_table("expand_perm_table32", 32);
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StubRoutines::x86::_expand_perm_table64 = generate_expand_perm_table("expand_perm_table64", 64);
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}
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if (VM_Version::supports_avx2() && !VM_Version::supports_avx512_vpopcntdq()) {
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// lut implementation influenced by counting 1s algorithm from section 5-1 of Hackers' Delight.
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StubRoutines::x86::_vector_popcount_lut = generate_popcount_avx_lut("popcount_lut");
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2003, 2023, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -99,6 +99,10 @@ class StubGenerator: public StubCodeGenerator {
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address generate_fp_mask(const char *stub_name, int64_t mask);
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address generate_compress_perm_table(const char *stub_name, int32_t esize);
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address generate_expand_perm_table(const char *stub_name, int32_t esize);
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address generate_vector_mask(const char *stub_name, int64_t mask);
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address generate_vector_byte_perm_mask(const char *stub_name);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013, 2023, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2013, 2024, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -82,6 +82,10 @@ address StubRoutines::x86::_join_0_1_base64 = nullptr;
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address StubRoutines::x86::_join_1_2_base64 = nullptr;
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address StubRoutines::x86::_join_2_3_base64 = nullptr;
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address StubRoutines::x86::_decoding_table_base64 = nullptr;
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address StubRoutines::x86::_compress_perm_table32 = nullptr;
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address StubRoutines::x86::_compress_perm_table64 = nullptr;
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address StubRoutines::x86::_expand_perm_table32 = nullptr;
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address StubRoutines::x86::_expand_perm_table64 = nullptr;
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#endif
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address StubRoutines::x86::_pshuffle_byte_flip_mask_addr = nullptr;
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013, 2023, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2013, 2024, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -37,7 +37,7 @@ enum platform_dependent_constants {
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_continuation_stubs_code_size = 1000 LP64_ONLY(+1000),
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// AVX512 intrinsics add more code in 64-bit VM,
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// Windows have more code to save/restore registers
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_compiler_stubs_code_size = 20000 LP64_ONLY(+32000) WINDOWS_ONLY(+2000),
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_compiler_stubs_code_size = 20000 LP64_ONLY(+39000) WINDOWS_ONLY(+2000),
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_final_stubs_code_size = 10000 LP64_ONLY(+20000) WINDOWS_ONLY(+2000) ZGC_ONLY(+20000)
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};
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@ -58,6 +58,10 @@ class x86 {
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static address _float_sign_flip;
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static address _double_sign_mask;
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static address _double_sign_flip;
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static address _compress_perm_table32;
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static address _compress_perm_table64;
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static address _expand_perm_table32;
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static address _expand_perm_table64;
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public:
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@ -338,6 +342,10 @@ class x86 {
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static address base64_decoding_table_addr() { return _decoding_table_base64; }
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static address base64_AVX2_decode_tables_addr() { return _avx2_decode_tables_base64; }
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static address base64_AVX2_decode_LUT_tables_addr() { return _avx2_decode_lut_tables_base64; }
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static address compress_perm_table32() { return _compress_perm_table32; }
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static address compress_perm_table64() { return _compress_perm_table64; }
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static address expand_perm_table32() { return _expand_perm_table32; }
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static address expand_perm_table64() { return _expand_perm_table64; }
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#endif
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static address pshuffle_byte_flip_mask_addr() { return _pshuffle_byte_flip_mask_addr; }
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static address arrays_hashcode_powers_of_31() { return (address)_arrays_hashcode_powers_of_31; }
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@ -44,4 +44,3 @@ address StubRoutines::x86::_float_sign_mask = nullptr;
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address StubRoutines::x86::_float_sign_flip = nullptr;
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address StubRoutines::x86::_double_sign_mask = nullptr;
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address StubRoutines::x86::_double_sign_flip = nullptr;
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@ -1425,6 +1425,8 @@ bool Matcher::match_rule_supported(int opcode) {
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return false;
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}
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break;
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case Op_CompressV:
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case Op_ExpandV:
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case Op_PopCountVL:
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if (UseAVX < 2) {
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return false;
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@ -1659,12 +1661,6 @@ bool Matcher::match_rule_supported(int opcode) {
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return false;
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}
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break;
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case Op_CompressV:
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case Op_ExpandV:
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if (!VM_Version::supports_avx512vl()) {
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return false;
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}
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break;
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case Op_SqrtF:
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if (UseSSE < 1) {
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return false;
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@ -1952,13 +1948,12 @@ bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
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if (is_subword_type(bt) && !VM_Version::supports_avx512_vbmi2()) {
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return false;
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}
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if (!is_LP64 && !VM_Version::supports_avx512vl() && size_in_bits < 512) {
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return false;
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}
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if (size_in_bits < 128 ) {
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return false;
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}
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if (size_in_bits < 512 && !VM_Version::supports_avx512vl()) {
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return false;
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}
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break;
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case Op_VectorLongToMask:
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if (UseAVX < 1 || !is_LP64) {
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return false;
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@ -9178,8 +9173,26 @@ instruct vmask_first_or_last_true_avx(rRegI dst, vec mask, immI size, rRegL tmp,
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%}
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// --------------------------------- Compress/Expand Operations ---------------------------
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#ifdef _LP64
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instruct vcompress_reg_avx(vec dst, vec src, vec mask, rRegI rtmp, rRegL rscratch, vec perm, vec xtmp, rFlagsReg cr) %{
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predicate(!VM_Version::supports_avx512vl() && Matcher::vector_length_in_bytes(n) <= 32);
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match(Set dst (CompressV src mask));
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match(Set dst (ExpandV src mask));
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effect(TEMP_DEF dst, TEMP perm, TEMP xtmp, TEMP rtmp, TEMP rscratch, KILL cr);
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format %{ "vector_compress $dst, $src, $mask \t!using $xtmp, $rtmp, $rscratch and $perm as TEMP" %}
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ins_encode %{
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int opcode = this->ideal_Opcode();
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int vlen_enc = vector_length_encoding(this);
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vector_compress_expand_avx2(opcode, $dst$$XMMRegister, $src$$XMMRegister, $mask$$XMMRegister, $rtmp$$Register,
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$rscratch$$Register, $perm$$XMMRegister, $xtmp$$XMMRegister, bt, vlen_enc);
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%}
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ins_pipe( pipe_slow );
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%}
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#endif
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instruct vcompress_expand_reg_evex(vec dst, vec src, kReg mask) %{
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predicate(VM_Version::supports_avx512vl() || Matcher::vector_length_in_bytes(n) == 64);
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match(Set dst (CompressV src mask));
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match(Set dst (ExpandV src mask));
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format %{ "vector_compress_expand $dst, $src, $mask" %}
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@ -0,0 +1,185 @@
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/*
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* Copyright (c) 2024, Oracle and/or its affiliates. All rights reserved.
|
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
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* version 2 for more details (a copy is included in the LICENSE file that
|
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
|
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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package org.openjdk.bench.jdk.incubator.vector;
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import java.util.concurrent.TimeUnit;
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import java.util.Random;
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import jdk.incubator.vector.*;
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import org.openjdk.jmh.annotations.*;
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import org.openjdk.jmh.infra.Blackhole;
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@OutputTimeUnit(TimeUnit.MILLISECONDS)
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@State(Scope.Thread)
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@Fork(jvmArgsPrepend = {"--add-modules=jdk.incubator.vector", "-XX:UseAVX=2"})
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public class ColumnFilterBenchmark {
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@Param({"1024", "2047", "4096"})
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int size;
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float [] floatinCol;
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float [] floatoutCol;
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float fpivot;
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double [] doubleinCol;
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double [] doubleoutCol;
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double dpivot;
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|
||||
int [] intinCol;
|
||||
int [] intoutCol;
|
||||
int ipivot;
|
||||
|
||||
long [] longinCol;
|
||||
long [] longoutCol;
|
||||
long lpivot;
|
||||
|
||||
static final VectorSpecies<Float> fspecies = FloatVector.SPECIES_256;
|
||||
static final VectorSpecies<Double> dspecies = DoubleVector.SPECIES_256;
|
||||
static final VectorSpecies<Integer> ispecies = IntVector.SPECIES_256;
|
||||
static final VectorSpecies<Long> lspecies = LongVector.SPECIES_256;
|
||||
|
||||
@Setup(Level.Trial)
|
||||
public void BmSetup() {
|
||||
Random r = new Random(2048);
|
||||
|
||||
floatinCol = new float[size];
|
||||
floatoutCol = new float[size];
|
||||
fpivot = (float) (size / 2);
|
||||
doubleinCol = new double[size];
|
||||
doubleoutCol = new double[size];
|
||||
dpivot = (double) (size / 2);
|
||||
intinCol = new int[size];
|
||||
intoutCol = new int[size];
|
||||
ipivot = size / 2;
|
||||
longinCol = new long[size];
|
||||
longoutCol = new long[size];
|
||||
lpivot = size / 2;
|
||||
|
||||
for (int i = 4; i < size; i++) {
|
||||
floatinCol[i] = r.nextFloat() * size;
|
||||
doubleinCol[i] = r.nextDouble() * size;
|
||||
intinCol[i] = r.nextInt(size);
|
||||
longinCol[i] = (long)intinCol[i];
|
||||
}
|
||||
}
|
||||
|
||||
@Benchmark
|
||||
public void fuzzyFilterIntColumn() {
|
||||
int i = 0;
|
||||
int j = 0;
|
||||
long maskctr = 1;
|
||||
int endIndex = ispecies.loopBound(size);
|
||||
for (; i < endIndex; i += ispecies.length()) {
|
||||
IntVector vec = IntVector.fromArray(ispecies, intinCol, i);
|
||||
VectorMask<Integer> pred = VectorMask.fromLong(ispecies, maskctr++);
|
||||
vec.compress(pred).intoArray(intoutCol, j);
|
||||
j += pred.trueCount();
|
||||
}
|
||||
}
|
||||
|
||||
@Benchmark
|
||||
public void fuzzyFilterLongColumn() {
|
||||
int i = 0;
|
||||
int j = 0;
|
||||
long maskctr = 1;
|
||||
int endIndex = lspecies.loopBound(size);
|
||||
for (; i < endIndex; i += lspecies.length()) {
|
||||
LongVector vec = LongVector.fromArray(lspecies, longinCol, i);
|
||||
VectorMask<Long> pred = VectorMask.fromLong(lspecies, maskctr++);
|
||||
vec.compress(pred).intoArray(longoutCol, j);
|
||||
j += pred.trueCount();
|
||||
}
|
||||
}
|
||||
|
||||
@Benchmark
|
||||
public void filterIntColumn() {
|
||||
int i = 0;
|
||||
int j = 0;
|
||||
int endIndex = ispecies.loopBound(size);
|
||||
for (; i < endIndex; i += ispecies.length()) {
|
||||
IntVector vec = IntVector.fromArray(ispecies, intinCol, i);
|
||||
VectorMask<Integer> pred = vec.compare(VectorOperators.GT, ipivot);
|
||||
vec.compress(pred).intoArray(intoutCol, j);
|
||||
j += pred.trueCount();
|
||||
}
|
||||
for (; i < endIndex; i++) {
|
||||
if (intinCol[i] > ipivot) {
|
||||
intoutCol[j++] = intinCol[i];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@Benchmark
|
||||
public void filterLongColumn() {
|
||||
int i = 0;
|
||||
int j = 0;
|
||||
int endIndex = lspecies.loopBound(size);
|
||||
for (; i < endIndex; i += lspecies.length()) {
|
||||
LongVector vec = LongVector.fromArray(lspecies, longinCol, i);
|
||||
VectorMask<Long> pred = vec.compare(VectorOperators.GT, lpivot);
|
||||
vec.compress(pred).intoArray(longoutCol, j);
|
||||
j += pred.trueCount();
|
||||
}
|
||||
for (; i < endIndex; i++) {
|
||||
if (longinCol[i] > lpivot) {
|
||||
longoutCol[j++] = longinCol[i];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@Benchmark
|
||||
public void filterFloatColumn() {
|
||||
int i = 0;
|
||||
int j = 0;
|
||||
int endIndex = fspecies.loopBound(size);
|
||||
for (; i < endIndex; i += fspecies.length()) {
|
||||
FloatVector vec = FloatVector.fromArray(fspecies, floatinCol, i);
|
||||
VectorMask<Float> pred = vec.compare(VectorOperators.GT, fpivot);
|
||||
vec.compress(pred).intoArray(floatoutCol, j);
|
||||
j += pred.trueCount();
|
||||
}
|
||||
for (; i < endIndex; i++) {
|
||||
if (floatinCol[i] > fpivot) {
|
||||
floatoutCol[j++] = floatinCol[i];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@Benchmark
|
||||
public void filterDoubleColumn() {
|
||||
int i = 0;
|
||||
int j = 0;
|
||||
int endIndex = dspecies.loopBound(size);
|
||||
for (; i < endIndex; i += dspecies.length()) {
|
||||
DoubleVector vec = DoubleVector.fromArray(dspecies, doubleinCol, i);
|
||||
VectorMask<Double> pred = vec.compare(VectorOperators.GT, dpivot);
|
||||
vec.compress(pred).intoArray(doubleoutCol, j);
|
||||
j += pred.trueCount();
|
||||
}
|
||||
for (; i < endIndex; i++) {
|
||||
if (doubleinCol[i] > dpivot) {
|
||||
doubleoutCol[j++] = doubleinCol[i];
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user