8249189: AARCH64: more L2I conversions can be skipped
Reviewed-by: aph
This commit is contained in:
Boris Ulasevich
parent
890ca6ea2c
commit
77c4adbeb5
@ -4053,6 +4053,18 @@ operand immI_bitmask()
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interface(CONST_INTER);
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%}
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operand immL_positive_bitmaskI()
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%{
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predicate((n->get_long() != 0)
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&& ((julong)n->get_long() < 0x80000000ULL)
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&& is_power_of_2(n->get_long() + 1));
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match(ConL);
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op_cost(0);
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format %{ %}
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interface(CONST_INTER);
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%}
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// Scale values for scaled offset addressing modes (up to long but not quad)
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operand immIScale()
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%{
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@ -12149,6 +12161,50 @@ instruct ubfizL(iRegLNoSp dst, iRegL src, immI lshift, immL_bitmask mask)
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ins_pipe(ialu_reg_shift);
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%}
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// This pattern is automatically generated from aarch64_ad.m4
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// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
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// We can use ubfiz when masking by a positive number and then left shifting the result.
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// We know that the mask is positive because immI_bitmask guarantees it.
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instruct ubfizwIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
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%{
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match(Set dst (ConvI2L (LShiftI (AndI src mask) lshift)));
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predicate((exact_log2(n->in(1)->in(1)->in(2)->get_int() + 1) + (n->in(1)->in(2)->get_int() & 31)) <= 31);
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ins_cost(INSN_COST);
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format %{ "ubfizw $dst, $src, $lshift, $mask" %}
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ins_encode %{
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int lshift = $lshift$$constant & 31;
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intptr_t mask = $mask$$constant;
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int width = exact_log2(mask+1);
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__ ubfizw(as_Register($dst$$reg),
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as_Register($src$$reg), lshift, width);
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%}
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ins_pipe(ialu_reg_shift);
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%}
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// This pattern is automatically generated from aarch64_ad.m4
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// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
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// We can use ubfiz when masking by a positive number and then left shifting the result.
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// We know that the mask is positive because immL_bitmask guarantees it.
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instruct ubfizLConvL2I(iRegINoSp dst, iRegL src, immI lshift, immL_positive_bitmaskI mask)
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%{
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match(Set dst (ConvL2I (LShiftL (AndL src mask) lshift)));
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predicate((exact_log2_long(n->in(1)->in(1)->in(2)->get_long() + 1) + (n->in(1)->in(2)->get_int() & 63)) <= 31);
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ins_cost(INSN_COST);
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format %{ "ubfiz $dst, $src, $lshift, $mask" %}
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ins_encode %{
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int lshift = $lshift$$constant & 63;
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intptr_t mask = $mask$$constant;
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int width = exact_log2_long(mask+1);
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__ ubfiz(as_Register($dst$$reg),
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as_Register($src$$reg), lshift, width);
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%}
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ins_pipe(ialu_reg_shift);
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%}
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// This pattern is automatically generated from aarch64_ad.m4
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// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
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@ -12174,6 +12230,27 @@ instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask
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// This pattern is automatically generated from aarch64_ad.m4
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// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
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// If there is a convert L to I block between and AndL and a LShiftI, we can also match ubfiz
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instruct ubfizLConvL2Ix(iRegINoSp dst, iRegL src, immI lshift, immL_positive_bitmaskI mask)
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%{
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match(Set dst (LShiftI (ConvL2I (AndL src mask)) lshift));
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predicate((exact_log2_long(n->in(1)->in(1)->in(2)->get_long() + 1) + (n->in(2)->get_int() & 31)) <= 31);
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ins_cost(INSN_COST);
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format %{ "ubfiz $dst, $src, $lshift, $mask" %}
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ins_encode %{
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int lshift = $lshift$$constant & 31;
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intptr_t mask = $mask$$constant;
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int width = exact_log2(mask+1);
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__ ubfiz(as_Register($dst$$reg),
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as_Register($src$$reg), lshift, width);
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%}
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ins_pipe(ialu_reg_shift);
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%}
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// This pattern is automatically generated from aarch64_ad.m4
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// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
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// Can skip int2long conversions after AND with small bitmask
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instruct ubfizIConvI2LAndI(iRegLNoSp dst, iRegI src, immI_bitmask msk)
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%{
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@ -237,39 +237,45 @@ define(`UBFIZ_INSN', `// This pattern is automatically generated from aarch64_ad
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// We can use ubfiz when masking by a positive number and then left shifting the result.
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// We know that the mask is positive because imm$1_bitmask guarantees it.
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instruct $2$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI lshift, imm$1_bitmask mask)
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instruct $3$1$8(iReg$2NoSp dst, iReg$1`'ORL2I($1) src, immI lshift, $7 mask)
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%{
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match(Set dst (LShift$1 (And$1 src mask) lshift));
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predicate((exact_log2$5(n->in(1)->in(2)->get_$4() + 1) + (n->in(2)->get_int() & $3)) <= ($3 + 1));
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ifelse($8,,
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match(Set dst (LShift$1 (And$1 src mask) lshift));,
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match(Set dst ($8 (LShift$1 (And$1 src mask) lshift)));)
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ifelse($8,,
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predicate(($6(n->in(1)->in(2)->get_$5() + 1) + (n->in(2)->get_int() & $4)) <= ($4 + 1));,
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predicate(($6(n->in(1)->in(1)->in(2)->get_$5() + 1) + (n->in(1)->in(2)->get_int() & $4)) <= 31);)
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ins_cost(INSN_COST);
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format %{ "$2 $dst, $src, $lshift, $mask" %}
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format %{ "$3 $dst, $src, $lshift, $mask" %}
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ins_encode %{
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int lshift = $lshift$$constant & $3;
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int lshift = $lshift$$constant & $4;
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intptr_t mask = $mask$$constant;
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int width = exact_log2$5(mask+1);
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__ $2(as_Register($dst$$reg),
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int width = $6(mask+1);
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__ $3(as_Register($dst$$reg),
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as_Register($src$$reg), lshift, width);
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%}
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ins_pipe(ialu_reg_shift);
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%}
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')
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UBFIZ_INSN(I, ubfizw, 31, int)
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UBFIZ_INSN(L, ubfiz, 63, long, _long)
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UBFIZ_INSN(I, I, ubfizw, 31, int, exact_log2, immI_bitmask)
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UBFIZ_INSN(L, L, ubfiz, 63, long, exact_log2_long, immL_bitmask)
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UBFIZ_INSN(I, L, ubfizw, 31, int, exact_log2, immI_bitmask, ConvI2L)
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UBFIZ_INSN(L, I, ubfiz, 63, long, exact_log2_long, immL_positive_bitmaskI, ConvL2I)
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// This pattern is automatically generated from aarch64_ad.m4
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define(`BFX1_INSN', `// This pattern is automatically generated from aarch64_ad.m4
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// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
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// If there is a convert I to L block between and AndI and a LShiftL, we can also match ubfiz
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instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
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// If there is a convert $1 to $2 block between and And$1 and a LShift$2, we can also match ubfiz
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instruct ubfiz$1Conv$3$9(iReg$2NoSp dst, iReg$1`'ORL2I($1) src, immI lshift, $8 mask)
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%{
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match(Set dst (LShiftL (ConvI2L (AndI src mask)) lshift));
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predicate((exact_log2(n->in(1)->in(1)->in(2)->get_int() + 1) + (n->in(2)->get_int() & 63)) <= (63 + 1));
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match(Set dst (LShift$2 (Conv$3 (And$1 src mask)) lshift));
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predicate(($4(n->in(1)->in(1)->in(2)->$5() + 1) + (n->in(2)->get_int() & $6)) <= $7);
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ins_cost(INSN_COST);
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format %{ "ubfiz $dst, $src, $lshift, $mask" %}
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ins_encode %{
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int lshift = $lshift$$constant & 63;
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int lshift = $lshift$$constant & $6;
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intptr_t mask = $mask$$constant;
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int width = exact_log2(mask+1);
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__ ubfiz(as_Register($dst$$reg),
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@ -277,7 +283,9 @@ instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask
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%}
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ins_pipe(ialu_reg_shift);
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%}
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')dnl
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BFX1_INSN(I, L, I2L, exact_log2, get_int, 63, (63 + 1), immI_bitmask)
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BFX1_INSN(L, I, L2I, exact_log2_long, get_long, 31, 31, immL_positive_bitmaskI, x)
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// This pattern is automatically generated from aarch64_ad.m4
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// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
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