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8342715: x86 unused orw instruction encoding could be removed

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Reviewed-by: sviswanathan, jbhateja, kvn
This commit is contained in:
hanklo6 2024-10-21 21:16:26 +00:00 committed by Sandhya Viswanathan
parent 5a4b180965
commit 8276a41958
2 changed files with 0 additions and 6 deletions
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5
src/hotspot/cpu/x86/assembler_x86.cpp
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@ -4439,11 +4439,6 @@ void Assembler::enotl(Register dst, Register src) {
emit_int16((unsigned char)0xF7, (0xD0 | encode)); emit_int16((unsigned char)0xF7, (0xD0 | encode));
} }
void Assembler::orw(Register dst, Register src) {
(void)prefix_and_encode(dst->encoding(), src->encoding());
emit_arith(0x0B, 0xC0, dst, src);
}
void Assembler::eorw(Register dst, Register src1, Register src2, bool no_flags) { void Assembler::eorw(Register dst, Register src1, Register src2, bool no_flags) {
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); (void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);

1
src/hotspot/cpu/x86/assembler_x86.hpp
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@ -1901,7 +1901,6 @@ private:
#endif #endif
void btq(Register dst, Register src); void btq(Register dst, Register src);
void orw(Register dst, Register src);
void eorw(Register dst, Register src1, Register src2, bool no_flags); void eorw(Register dst, Register src1, Register src2, bool no_flags);
void orl(Address dst, int32_t imm32); void orl(Address dst, int32_t imm32);