8212481: PPC64: Enable POWER9 CPU detection
Reviewed-by: mdoerr, simonis
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307ba484e1
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84a22b6b36
@ -535,6 +535,9 @@ class Assembler : public AbstractAssembler {
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XVMULSP_OPCODE = (60u << OPCODE_SHIFT | 80u << 3),
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XVMULDP_OPCODE = (60u << OPCODE_SHIFT | 112u << 3),
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// Deliver A Random Number (introduced with POWER9)
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DARN_OPCODE = (31u << OPCODE_SHIFT | 755u << 1),
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// Vector Permute and Formatting
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VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
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VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ),
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@ -1072,6 +1075,7 @@ class Assembler : public AbstractAssembler {
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static int frt( int x) { return opp_u_field(x, 10, 6); }
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static int fxm( int x) { return opp_u_field(x, 19, 12); }
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static int l10( int x) { return opp_u_field(x, 10, 10); }
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static int l14( int x) { return opp_u_field(x, 15, 14); }
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static int l15( int x) { return opp_u_field(x, 15, 15); }
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static int l910( int x) { return opp_u_field(x, 10, 9); }
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static int e1215( int x) { return opp_u_field(x, 15, 12); }
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@ -2220,6 +2224,9 @@ class Assembler : public AbstractAssembler {
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inline void mtfprwa( FloatRegister d, Register a);
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inline void mffprd( Register a, FloatRegister d);
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// Deliver A Random Number (introduced with POWER9)
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inline void darn( Register d, int l = 1 /*L=CRN*/);
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// AES (introduced with Power 8)
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inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2002, 2017, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2017 SAP SE. All rights reserved.
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* Copyright (c) 2002, 2018, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2018 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -979,6 +979,9 @@ inline void Assembler::tsuspend_() { emit_int32( TS
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inline void Assembler::tresume_() { emit_int32( TSR_OPCODE | /*L=1*/ 1u << (31-10) | rc(1)); }
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inline void Assembler::tcheck(int f) { emit_int32( TCHECK_OPCODE | bf(f)); }
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// Deliver A Random Number (introduced with POWER9)
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inline void Assembler::darn(Register d, int l /* =1 */) { emit_int32( DARN_OPCODE | rt(d) | l14(l)); }
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// ra0 version
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inline void Assembler::lwzx( Register d, Register s2) { emit_int32( LWZX_OPCODE | rt(d) | rb(s2));}
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inline void Assembler::lwz( Register d, int si16 ) { emit_int32( LWZ_OPCODE | rt(d) | d1(si16));}
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@ -63,7 +63,9 @@ void VM_Version::initialize() {
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// If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
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if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
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if (VM_Version::has_lqarx()) {
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if (VM_Version::has_darn()) {
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FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 9);
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} else if (VM_Version::has_lqarx()) {
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FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
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} else if (VM_Version::has_popcntw()) {
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FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
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@ -78,6 +80,7 @@ void VM_Version::initialize() {
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bool PowerArchitecturePPC64_ok = false;
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switch (PowerArchitecturePPC64) {
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case 9: if (!VM_Version::has_darn() ) break;
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case 8: if (!VM_Version::has_lqarx() ) break;
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case 7: if (!VM_Version::has_popcntw()) break;
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case 6: if (!VM_Version::has_cmpb() ) break;
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@ -131,12 +134,11 @@ void VM_Version::initialize() {
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// Create and print feature-string.
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char buf[(num_features+1) * 16]; // Max 16 chars per feature.
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jio_snprintf(buf, sizeof(buf),
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"ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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"ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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(has_fsqrt() ? " fsqrt" : ""),
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(has_isel() ? " isel" : ""),
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(has_lxarxeh() ? " lxarxeh" : ""),
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(has_cmpb() ? " cmpb" : ""),
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//(has_mftgpr()? " mftgpr" : ""),
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(has_popcntb() ? " popcntb" : ""),
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(has_popcntw() ? " popcntw" : ""),
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(has_fcfids() ? " fcfids" : ""),
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@ -149,7 +151,8 @@ void VM_Version::initialize() {
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(has_ldbrx() ? " ldbrx" : ""),
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(has_stdbrx() ? " stdbrx" : ""),
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(has_vshasig() ? " sha" : ""),
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(has_tm() ? " rtm" : "")
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(has_tm() ? " rtm" : ""),
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(has_darn() ? " darn" : "")
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// Make sure number of %s matches num_features!
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);
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_features_string = os::strdup(buf);
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@ -663,6 +666,8 @@ void VM_Version::determine_features() {
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a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[14] -> ldbrx
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a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> stdbrx
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a->vshasigmaw(VR0, VR1, 1, 0xF); // code[16] -> vshasig
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// rtm is determined by OS
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a->darn(R7); // code[17] -> darn
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a->blr();
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// Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
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@ -714,6 +719,8 @@ void VM_Version::determine_features() {
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if (code[feature_cntr++]) features |= ldbrx_m;
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if (code[feature_cntr++]) features |= stdbrx_m;
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if (code[feature_cntr++]) features |= vshasig_m;
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// feature rtm_m is determined by OS
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if (code[feature_cntr++]) features |= darn_m;
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// Print the detection code.
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if (PrintAssembly) {
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2017 SAP SE. All rights reserved.
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* Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2018 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -50,6 +50,7 @@ protected:
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stdbrx,
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vshasig,
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rtm,
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darn,
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num_features // last entry to count features
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};
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enum Feature_Flag_Set {
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@ -72,6 +73,7 @@ protected:
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stdbrx_m = (1 << stdbrx ),
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vshasig_m = (1 << vshasig),
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rtm_m = (1 << rtm ),
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darn_m = (1 << darn ),
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all_features_m = (unsigned long)-1
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};
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@ -108,9 +110,10 @@ public:
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static bool has_ldbrx() { return (_features & ldbrx_m) != 0; }
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static bool has_stdbrx() { return (_features & stdbrx_m) != 0; }
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static bool has_vshasig() { return (_features & vshasig_m) != 0; }
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static bool has_mtfprd() { return has_vpmsumb(); } // alias for P8
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// OS feature support
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static bool has_tm() { return (_features & rtm_m) != 0; }
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static bool has_darn() { return (_features & darn_m) != 0; }
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static bool has_mtfprd() { return has_vpmsumb(); } // alias for P8
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// Assembler testing
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static void allow_all();
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