From 8cb9b479c529c058aee50f83920db650b0c18045 Mon Sep 17 00:00:00 2001 From: Robbin Ehn Date: Thu, 15 Feb 2024 09:17:52 +0000 Subject: [PATCH] 8321282: RISC-V: SpinPause() not implemented Reviewed-by: luhenry, fbredberg, fyang --- src/hotspot/os_cpu/linux_riscv/os_linux_riscv.cpp | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/hotspot/os_cpu/linux_riscv/os_linux_riscv.cpp b/src/hotspot/os_cpu/linux_riscv/os_linux_riscv.cpp index 3d923c03094..9f13e2bdd2c 100644 --- a/src/hotspot/os_cpu/linux_riscv/os_linux_riscv.cpp +++ b/src/hotspot/os_cpu/linux_riscv/os_linux_riscv.cpp @@ -38,6 +38,7 @@ #include "prims/jvm_misc.hpp" #include "runtime/arguments.hpp" #include "runtime/frame.inline.hpp" +#include "runtime/globals.hpp" #include "runtime/interfaceSupport.inline.hpp" #include "runtime/java.hpp" #include "runtime/javaCalls.hpp" @@ -405,6 +406,14 @@ static inline void atomic_copy64(const volatile void *src, volatile void *dst) { extern "C" { int SpinPause() { + if (UseZihintpause) { + // PAUSE is encoded as a FENCE instruction with pred=W, succ=0, fm=0, rd=x0, and rs1=x0. + // To do: __asm__ volatile("pause " : : : ); + // Since we're currently not passing '-march=..._zihintpause' to the compiler, + // it will not recognize the "pause" instruction, hence the hard-coded instruction. + __asm__ volatile(".word 0x0100000f " : : : ); + return 1; + } return 0; }