8266332: Adler32 intrinsic for x86 64-bit platforms
Co-authored-by: Xubo Zhang <xubo.zhang@intel.com> Co-authored-by: Greg B Tucker <greg.b.tucker@intel.com> Co-authored-by: Pengfei Li <pli@openjdk.org> Reviewed-by: sviswanathan, jbhateja, kvn, neliasso
This commit is contained in:
Xubo Zhang
Vladimir Kozlov
parent
b961f2535c
commit
8e3549fc73
@ -8030,6 +8030,18 @@ void Assembler::vbroadcastsd(XMMRegister dst, Address src, int vector_len) {
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emit_operand(dst, src);
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}
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void Assembler::vbroadcastf128(XMMRegister dst, Address src, int vector_len) {
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assert(VM_Version::supports_avx(), "");
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assert(vector_len == AVX_256bit, "");
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assert(dst != xnoreg, "sanity");
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InstructionMark im(this);
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InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
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attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
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// swap src<->dst for encoding
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vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
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emit_int8(0x1A);
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emit_operand(dst, src);
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}
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// gpr source broadcast forms
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@ -2442,11 +2442,12 @@ private:
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void evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len);
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void evbroadcasti64x2(XMMRegister dst, Address src, int vector_len);
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// scalar single/double precision replicate
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// scalar single/double/128bit precision replicate
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void vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
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void vbroadcastss(XMMRegister dst, Address src, int vector_len);
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void vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
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void vbroadcastsd(XMMRegister dst, Address src, int vector_len);
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void vbroadcastf128(XMMRegister dst, Address src, int vector_len);
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// gpr sourced byte/word/dword/qword replicate
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void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
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@ -3231,6 +3231,16 @@ void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int
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Assembler::vpmullw(dst, nds, src, vector_len);
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}
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void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
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assert((UseAVX > 0), "AVX support is needed");
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if (reachable(src)) {
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Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
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} else {
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lea(scratch_reg, src);
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Assembler::vpmulld(dst, nds, Address(scratch_reg, 0), vector_len);
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}
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}
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void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
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assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
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Assembler::vpsubb(dst, nds, src, vector_len);
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@ -1307,6 +1307,13 @@ public:
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void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
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void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
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void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
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Assembler::vpmulld(dst, nds, src, vector_len);
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};
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void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
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Assembler::vpmulld(dst, nds, src, vector_len);
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}
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void vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg);
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void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
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void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
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@ -1764,6 +1771,7 @@ public:
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void kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos,
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Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
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Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup);
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void updateBytesAdler32(Register adler32, Register buf, Register length, XMMRegister shuf0, XMMRegister shuf1, ExternalAddress scale);
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#endif // _LP64
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// CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
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211
src/hotspot/cpu/x86/macroAssembler_x86_adler.cpp
Normal file
211
src/hotspot/cpu/x86/macroAssembler_x86_adler.cpp
Normal file
@ -0,0 +1,211 @@
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/*
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* Copyright (c) 2021, Intel Corporation.
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*
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#include "precompiled.hpp"
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#include "asm/assembler.hpp"
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#include "asm/assembler.inline.hpp"
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#include "runtime/stubRoutines.hpp"
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#include "macroAssembler_x86.hpp"
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#ifdef _LP64
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void MacroAssembler::updateBytesAdler32(Register init_d, Register data, Register size, XMMRegister yshuf0, XMMRegister yshuf1, ExternalAddress ascaletab)
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{
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const int LIMIT = 5552;
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const int BASE = 65521;
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const int CHUNKSIZE = 16;
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const int CHUNKSIZE_M1 = CHUNKSIZE - 1;
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const Register s = r11;
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const Register a_d = r12; //r12d
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const Register b_d = r8; //r8d
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const Register end = r13;
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const XMMRegister ya = xmm0;
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const XMMRegister yb = xmm1;
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const XMMRegister ydata0 = xmm2;
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const XMMRegister ydata1 = xmm3;
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const XMMRegister ysa = xmm4;
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const XMMRegister ydata = ysa;
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const XMMRegister ytmp0 = ydata0;
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const XMMRegister ytmp1 = ydata1;
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const XMMRegister ytmp2 = xmm5;
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const XMMRegister xa = xmm0;
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const XMMRegister xb = xmm1;
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const XMMRegister xtmp0 = xmm2;
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const XMMRegister xtmp1 = xmm3;
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const XMMRegister xsa = xmm4;
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const XMMRegister xtmp2 = xmm5;
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assert_different_registers(init_d, data, size, s, a_d, b_d, end, rax);
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Label SLOOP1, SLOOP1A, SKIP_LOOP_1A, FINISH, LT64, DO_FINAL, FINAL_LOOP, ZERO_SIZE, END;
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push(r12);
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push(r13);
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push(r14);
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movl(b_d, init_d); //adler
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shrl(b_d, 16);
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andl(init_d, 0xFFFF);
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cmpl(size, 32);
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jcc(Assembler::below, LT64);
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movdl(xa, init_d); //vmovd - 32bit
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vpxor(yb, yb, yb, Assembler::AVX_256bit);
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bind(SLOOP1);
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movl(s, LIMIT);
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cmpl(s, size);
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cmovl(Assembler::above, s, size); // s = min(size, LIMIT)
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lea(end, Address(s, data, Address::times_1, -CHUNKSIZE_M1));
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cmpptr(data, end);
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jcc(Assembler::aboveEqual, SKIP_LOOP_1A);
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align(32);
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bind(SLOOP1A);
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vbroadcastf128(ydata, Address(data, 0), Assembler::AVX_256bit);
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addptr(data, CHUNKSIZE);
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vpshufb(ydata0, ydata, yshuf0, Assembler::AVX_256bit);
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vpaddd(ya, ya, ydata0, Assembler::AVX_256bit);
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vpaddd(yb, yb, ya, Assembler::AVX_256bit);
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vpshufb(ydata1, ydata, yshuf1, Assembler::AVX_256bit);
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vpaddd(ya, ya, ydata1, Assembler::AVX_256bit);
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vpaddd(yb, yb, ya, Assembler::AVX_256bit);
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cmpptr(data, end);
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jcc(Assembler::below, SLOOP1A);
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bind(SKIP_LOOP_1A);
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addptr(end, CHUNKSIZE_M1);
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testl(s, CHUNKSIZE_M1);
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jcc(Assembler::notEqual, DO_FINAL);
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// either we're done, or we just did LIMIT
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subl(size, s);
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// reduce
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vpslld(yb, yb, 3, Assembler::AVX_256bit); //b is scaled by 8
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vpmulld(ysa, ya, ascaletab, Assembler::AVX_256bit, r14);
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// compute horizontal sums of ya, yb, ysa
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vextracti128(xtmp0, ya, 1);
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vextracti128(xtmp1, yb, 1);
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vextracti128(xtmp2, ysa, 1);
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vpaddd(xa, xa, xtmp0, Assembler::AVX_128bit);
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vpaddd(xb, xb, xtmp1, Assembler::AVX_128bit);
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vpaddd(xsa, xsa, xtmp2, Assembler::AVX_128bit);
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vphaddd(xa, xa, xa, Assembler::AVX_128bit);
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vphaddd(xb, xb, xb, Assembler::AVX_128bit);
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vphaddd(xsa, xsa, xsa, Assembler::AVX_128bit);
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vphaddd(xa, xa, xa, Assembler::AVX_128bit);
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vphaddd(xb, xb, xb, Assembler::AVX_128bit);
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vphaddd(xsa, xsa, xsa, Assembler::AVX_128bit);
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movdl(rax, xa);
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xorl(rdx, rdx);
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movl(rcx, BASE);
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divl(rcx); // divide edx:eax by ecx, quot->eax, rem->edx
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movl(a_d, rdx);
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vpsubd(xb, xb, xsa, Assembler::AVX_128bit);
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movdl(rax, xb);
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addl(rax, b_d);
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xorl(rdx, rdx);
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movl(rcx, BASE);
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divl(rcx); // divide edx:eax by ecx, quot->eax, rem->edx
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movl(b_d, rdx);
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testl(size, size);
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jcc(Assembler::zero, FINISH);
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// continue loop
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movdl(xa, a_d);
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vpxor(yb, yb, yb, Assembler::AVX_256bit);
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jmp(SLOOP1);
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bind(FINISH);
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movl(rax, b_d);
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shll(rax, 16);
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orl(rax, a_d);
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jmp(END);
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bind(LT64);
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movl(a_d, init_d);
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lea(end, Address(data, size, Address::times_1));
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testl(size, size);
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jcc(Assembler::notZero, FINAL_LOOP);
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jmp(ZERO_SIZE);
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// handle remaining 1...15 bytes
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bind(DO_FINAL);
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// reduce
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vpslld(yb, yb, 3, Assembler::AVX_256bit); //b is scaled by 8
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vpmulld(ysa, ya, ascaletab, Assembler::AVX_256bit, r14); //scaled a
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vextracti128(xtmp0, ya, 1);
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vextracti128(xtmp1, yb, 1);
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vextracti128(xtmp2, ysa, 1);
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vpaddd(xa, xa, xtmp0, Assembler::AVX_128bit);
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vpaddd(xb, xb, xtmp1, Assembler::AVX_128bit);
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vpaddd(xsa, xsa, xtmp2, Assembler::AVX_128bit);
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vphaddd(xa, xa, xa, Assembler::AVX_128bit);
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vphaddd(xb, xb, xb, Assembler::AVX_128bit);
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vphaddd(xsa, xsa, xsa, Assembler::AVX_128bit);
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vphaddd(xa, xa, xa, Assembler::AVX_128bit);
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vphaddd(xb, xb, xb, Assembler::AVX_128bit);
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vphaddd(xsa, xsa, xsa, Assembler::AVX_128bit);
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vpsubd(xb, xb, xsa, Assembler::AVX_128bit);
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movdl(a_d, xa);
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movdl(rax, xb);
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addl(b_d, rax);
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align(32);
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bind(FINAL_LOOP);
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movzbl(rax, Address(data, 0)); //movzx eax, byte[data]
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addl(a_d, rax);
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addptr(data, 1);
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addl(b_d, a_d);
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cmpptr(data, end);
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jcc(Assembler::below, FINAL_LOOP);
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bind(ZERO_SIZE);
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movl(rax, a_d);
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xorl(rdx, rdx);
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movl(rcx, BASE);
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divl(rcx); // div ecx -- divide edx:eax by ecx, quot->eax, rem->edx
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movl(a_d, rdx);
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movl(rax, b_d);
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xorl(rdx, rdx);
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movl(rcx, BASE);
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divl(rcx); // divide edx:eax by ecx, quot->eax, rem->edx
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shll(rdx, 16);
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orl(rdx, a_d);
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movl(rax, rdx);
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bind(END);
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pop(r14);
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pop(r13);
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pop(r12);
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}
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#endif
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@ -5790,6 +5790,47 @@ address generate_avx_ghash_processBlocks() {
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return start;
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}
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/***
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* Arguments:
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*
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* Inputs:
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* c_rarg0 - int adler
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* c_rarg1 - byte* buff
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* c_rarg2 - int len
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*
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* Output:
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* rax - int adler result
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*/
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address generate_updateBytesAdler32() {
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assert(UseAdler32Intrinsics, "need AVX2");
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__ align(CodeEntryAlignment);
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StubCodeMark mark(this, "StubRoutines", "updateBytesAdler32");
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address start = __ pc();
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const Register data = r9;
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const Register size = r10;
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const XMMRegister yshuf0 = xmm6;
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const XMMRegister yshuf1 = xmm7;
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assert_different_registers(c_rarg0, c_rarg1, c_rarg2, data, size);
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BLOCK_COMMENT("Entry:");
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__ enter(); // required for proper stackwalking of RuntimeStub frame
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__ vmovdqu(yshuf0, ExternalAddress((address) StubRoutines::x86::_adler32_shuf0_table), r9);
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__ vmovdqu(yshuf1, ExternalAddress((address) StubRoutines::x86::_adler32_shuf1_table), r9);
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__ movptr(data, c_rarg1); //data
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__ movl(size, c_rarg2); //length
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__ updateBytesAdler32(c_rarg0, data, size, yshuf0, yshuf1, ExternalAddress((address) StubRoutines::x86::_adler32_ascale_table));
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__ leave();
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__ ret(0);
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return start;
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}
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/**
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* Arguments:
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*
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@ -6754,6 +6795,11 @@ address generate_avx_ghash_processBlocks() {
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StubRoutines::_crc32c_table_addr = (address)StubRoutines::x86::_crc32c_table;
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StubRoutines::_updateBytesCRC32C = generate_updateBytesCRC32C(supports_clmul);
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}
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if (UseAdler32Intrinsics) {
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StubRoutines::_updateBytesAdler32 = generate_updateBytesAdler32();
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}
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if (UseLibmIntrinsic && InlineIntrinsics) {
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if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dsin) ||
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vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dcos) ||
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@ -224,6 +224,25 @@ juint StubRoutines::x86::_shuf_table_crc32_avx512[] =
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0x83828100UL, 0x87868584UL, 0x8b8a8988UL, 0x8f8e8d8cUL,
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0x03020100UL, 0x07060504UL, 0x0b0a0908UL, 0x000e0d0cUL
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};
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juint StubRoutines::x86::_adler32_ascale_table[] =
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{
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0x00000000UL, 0x00000001UL, 0x00000002UL, 0x00000003UL,
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0x00000004UL, 0x00000005UL, 0x00000006UL, 0x00000007UL
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};
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juint StubRoutines::x86::_adler32_shuf0_table[] =
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{
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0xFFFFFF00UL, 0xFFFFFF01UL, 0xFFFFFF02UL, 0xFFFFFF03UL,
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0xFFFFFF04UL, 0xFFFFFF05UL, 0xFFFFFF06UL, 0xFFFFFF07UL
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};
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juint StubRoutines::x86::_adler32_shuf1_table[] =
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{
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0xFFFFFF08UL, 0xFFFFFF09, 0xFFFFFF0AUL, 0xFFFFFF0BUL,
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0xFFFFFF0CUL, 0xFFFFFF0D, 0xFFFFFF0EUL, 0xFFFFFF0FUL
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};
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#endif // _LP64
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#define D 32
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@ -119,6 +119,9 @@ class x86 {
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static juint _crc_by128_masks_avx512[];
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static juint _crc_table_avx512[];
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static juint _shuf_table_crc32_avx512[];
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static juint _adler32_shuf0_table[];
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static juint _adler32_shuf1_table[];
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||||
static juint _adler32_ascale_table[];
|
||||
#endif // _LP64
|
||||
// table for CRC32C
|
||||
static juint* _crc32c_table;
|
||||
|
||||
@ -898,6 +898,24 @@ void VM_Version::get_processor_features() {
|
||||
FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
|
||||
}
|
||||
|
||||
#ifdef _LP64
|
||||
if (supports_avx2()) {
|
||||
if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
|
||||
UseAdler32Intrinsics = true;
|
||||
}
|
||||
} else if (UseAdler32Intrinsics) {
|
||||
if (!FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
|
||||
warning("Adler32 Intrinsics requires avx2 instructions (not available on this CPU)");
|
||||
}
|
||||
FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
|
||||
}
|
||||
#else
|
||||
if (UseAdler32Intrinsics) {
|
||||
warning("Adler32Intrinsics not available on this CPU.");
|
||||
FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (supports_sse4_2() && supports_clmul()) {
|
||||
if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
|
||||
UseCRC32CIntrinsics = true;
|
||||
@ -993,11 +1011,6 @@ void VM_Version::get_processor_features() {
|
||||
FLAG_SET_DEFAULT(UseSHA, false);
|
||||
}
|
||||
|
||||
if (UseAdler32Intrinsics) {
|
||||
warning("Adler32Intrinsics not available on this CPU.");
|
||||
FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
|
||||
}
|
||||
|
||||
if (!supports_rtm() && UseRTMLocking) {
|
||||
// Can't continue because UseRTMLocking affects UseBiasedLocking flag
|
||||
// setting during arguments processing. See use_biased_locking().
|
||||
|
||||
@ -93,6 +93,7 @@ bool vmIntrinsics::preserves_state(vmIntrinsics::ID id) {
|
||||
case vmIntrinsics::_updateCRC32:
|
||||
case vmIntrinsics::_updateBytesCRC32:
|
||||
case vmIntrinsics::_updateByteBufferCRC32:
|
||||
case vmIntrinsics::_updateBytesAdler32:
|
||||
case vmIntrinsics::_vectorizedMismatch:
|
||||
case vmIntrinsics::_fmaD:
|
||||
case vmIntrinsics::_fmaF:
|
||||
|
||||
@ -231,6 +231,7 @@ JVMCIObjectArray CompilerToVM::initialize_intrinsics(JVMCI_TRAPS) {
|
||||
X86_ONLY(do_intx_flag(UseAVX)) \
|
||||
do_bool_flag(UseBiasedLocking) \
|
||||
do_bool_flag(UseCRC32Intrinsics) \
|
||||
do_bool_flag(UseAdler32Intrinsics) \
|
||||
do_bool_flag(UseCompressedClassPointers) \
|
||||
do_bool_flag(UseCompressedOops) \
|
||||
X86_ONLY(do_bool_flag(UseCountLeadingZerosInstruction)) \
|
||||
|
||||
@ -574,6 +574,7 @@ typedef HashtableEntry<InstanceKlass*, mtClass> KlassHashtableEntry;
|
||||
static_field(StubRoutines, _crc_table_adr, address) \
|
||||
static_field(StubRoutines, _crc32c_table_addr, address) \
|
||||
static_field(StubRoutines, _updateBytesCRC32C, address) \
|
||||
static_field(StubRoutines, _updateBytesAdler32, address) \
|
||||
static_field(StubRoutines, _multiplyToLen, address) \
|
||||
static_field(StubRoutines, _squareToLen, address) \
|
||||
static_field(StubRoutines, _bigIntegerRightShiftWorker, address) \
|
||||
|
||||
62
test/micro/org/openjdk/bench/java/util/TestAdler32.java
Normal file
62
test/micro/org/openjdk/bench/java/util/TestAdler32.java
Normal file
@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 only, as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This code is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* version 2 for more details (a copy is included in the LICENSE file that
|
||||
* accompanied this code).
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License version
|
||||
* 2 along with this work; if not, write to the Free Software Foundation,
|
||||
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
|
||||
* or visit www.oracle.com if you need additional information or have any
|
||||
* questions.
|
||||
*/
|
||||
package org.openjdk.bench.java.util;
|
||||
|
||||
import java.util.Random;
|
||||
import java.util.concurrent.TimeUnit;
|
||||
import java.util.zip.Adler32;
|
||||
import org.openjdk.jmh.annotations.*;
|
||||
|
||||
@BenchmarkMode(Mode.AverageTime)
|
||||
@OutputTimeUnit(TimeUnit.MICROSECONDS)
|
||||
@State(Scope.Benchmark)
|
||||
@Fork(value = 2)
|
||||
@Warmup(iterations = 2, time = 30, timeUnit = TimeUnit.SECONDS)
|
||||
@Measurement(iterations = 3, time = 60, timeUnit = TimeUnit.SECONDS)
|
||||
|
||||
public class TestAdler32 {
|
||||
|
||||
private Adler32 adler32;
|
||||
private Random random;
|
||||
private byte[] bytes;
|
||||
|
||||
@Param({"64", "128", "256", "512", "1024", "2048", "4096", "8192", "16384", "32768", "65536"})
|
||||
private int count;
|
||||
|
||||
public TestAdler32() {
|
||||
adler32 = new Adler32();
|
||||
random = new Random(2147483648L);
|
||||
bytes = new byte[1000000];
|
||||
random.nextBytes(bytes);
|
||||
}
|
||||
|
||||
@Setup(Level.Iteration)
|
||||
public void setupBytes() {
|
||||
adler32.reset();
|
||||
}
|
||||
|
||||
@Benchmark
|
||||
public void testAdler32Update() {
|
||||
adler32.update(bytes, 0, count);
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user