8011415: CTW on Sparc: assert(lrg.lo_degree()) failed:
Increased the LRG AllStack mask size since the previous size was not big enough when compiling huge methods (60k+ nodes) Reviewed-by: kvn, roland, twisti
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@ -52,6 +52,7 @@ class PhaseChaitin;
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class LRG : public ResourceObj {
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class LRG : public ResourceObj {
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friend class VMStructs;
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friend class VMStructs;
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public:
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public:
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static const uint AllStack_size = 0xFFFFF; // This mask size is used to tell that the mask of this LRG supports stack positions
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enum { SPILL_REG=29999 }; // Register number of a spilled LRG
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enum { SPILL_REG=29999 }; // Register number of a spilled LRG
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double _cost; // 2 for loads/1 for stores times block freq
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double _cost; // 2 for loads/1 for stores times block freq
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@ -83,11 +84,18 @@ public:
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int degree() const { assert( _degree_valid , "" ); return _eff_degree; }
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int degree() const { assert( _degree_valid , "" ); return _eff_degree; }
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// Degree starts not valid and any change to the IFG neighbor
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// Degree starts not valid and any change to the IFG neighbor
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// set makes it not valid.
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// set makes it not valid.
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void set_degree( uint degree ) { _eff_degree = degree; debug_only(_degree_valid = 1;) }
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void set_degree( uint degree ) {
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_eff_degree = degree;
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debug_only(_degree_valid = 1;)
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assert(!_mask.is_AllStack() || (_mask.is_AllStack() && lo_degree()), "_eff_degree can't be bigger than AllStack_size - _num_regs if the mask supports stack registers");
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}
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// Made a change that hammered degree
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// Made a change that hammered degree
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void invalid_degree() { debug_only(_degree_valid=0;) }
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void invalid_degree() { debug_only(_degree_valid=0;) }
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// Incrementally modify degree. If it was correct, it should remain correct
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// Incrementally modify degree. If it was correct, it should remain correct
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void inc_degree( uint mod ) { _eff_degree += mod; }
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void inc_degree( uint mod ) {
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_eff_degree += mod;
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assert(!_mask.is_AllStack() || (_mask.is_AllStack() && lo_degree()), "_eff_degree can't be bigger than AllStack_size - _num_regs if the mask supports stack registers");
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}
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// Compute the degree between 2 live ranges
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// Compute the degree between 2 live ranges
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int compute_degree( LRG &l ) const;
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int compute_degree( LRG &l ) const;
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@ -95,9 +103,9 @@ private:
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RegMask _mask; // Allowed registers for this LRG
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RegMask _mask; // Allowed registers for this LRG
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uint _mask_size; // cache of _mask.Size();
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uint _mask_size; // cache of _mask.Size();
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public:
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public:
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int compute_mask_size() const { return _mask.is_AllStack() ? 65535 : _mask.Size(); }
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int compute_mask_size() const { return _mask.is_AllStack() ? AllStack_size : _mask.Size(); }
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void set_mask_size( int size ) {
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void set_mask_size( int size ) {
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assert((size == 65535) || (size == (int)_mask.Size()), "");
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assert((size == (int)AllStack_size) || (size == (int)_mask.Size()), "");
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_mask_size = size;
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_mask_size = size;
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#ifdef ASSERT
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#ifdef ASSERT
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_msize_valid=1;
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_msize_valid=1;
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@ -677,7 +677,7 @@ uint PhaseChaitin::build_ifg_physical( ResourceArea *a ) {
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} else { // Common case: size 1 bound removal
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} else { // Common case: size 1 bound removal
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if( lrg.mask().Member(r_reg) ) {
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if( lrg.mask().Member(r_reg) ) {
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lrg.Remove(r_reg);
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lrg.Remove(r_reg);
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lrg.set_mask_size(lrg.mask().is_AllStack() ? 65535:old_size-1);
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lrg.set_mask_size(lrg.mask().is_AllStack() ? LRG::AllStack_size : old_size - 1);
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}
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}
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}
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}
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// If 'l' goes completely dry, it must spill.
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// If 'l' goes completely dry, it must spill.
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