stan/jdk-24
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This commit is contained in:
Phil Race 2018-06-19 10:12:35 -07:00
commit 93c8d9bffd
4 changed files with 19 additions and 26 deletions

2
make/autoconf/flags-cflags.m4

@ -232,7 +232,7 @@ AC_DEFUN([FLAGS_SETUP_OPTIMIZATION],
C_O_FLAG_NORM="-xO2 -Wu,-O2~yz"
elif test "x$OPENJDK_TARGET_CPU_ARCH" = "xsparc"; then
C_O_FLAG_HIGHEST="-xO4 -Wc,-Qrm-s -Wc,-Qiselect-T0 \
-xprefetch=auto,explicit -xchip=ultra $CC_HIGHEST"
-xprefetch=auto,explicit $CC_HIGHEST"
C_O_FLAG_HI="-xO4 -Wc,-Qrm-s -Wc,-Qiselect-T0"
C_O_FLAG_NORM="-xO2 -Wc,-Qrm-s -Wc,-Qiselect-T0"
fi

2
make/hotspot/lib/JvmOverrideFiles.gmk

@ -74,6 +74,8 @@ ifeq ($(OPENJDK_TARGET_OS), linux)
else ifeq ($(OPENJDK_TARGET_OS), solaris)
ifneq ($(DEBUG_LEVEL), slowdebug)
# dev studio 12.6 workaround
BUILD_LIBJVM_arguments.cpp_OPTIMIZATION := LOW
# Workaround for a bug in dtrace. If ciEnv::post_compiled_method_load_event()
# is inlined, the resulting dtrace object file needs a reference to this
# function, whose symbol name is too long for dtrace. So disable inlining

9
src/hotspot/cpu/aarch64/assembler_aarch64.hpp

@ -2354,15 +2354,6 @@ public:
ushll(Vd, Ta, Vn, Tb, shift);
}
void uzp1(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T, int op = 0){
starti;
f(0, 31), f((T & 0x1), 30), f(0b001110, 29, 24), f((T >> 1), 23, 22), f(0, 21);
rf(Vm, 16), f(0, 15), f(op, 14), f(0b0110, 13, 10), rf(Vn, 5), rf(Vd, 0);
}
void uzp2(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T){
uzp1(Vd, Vn, Vm, T, 1);
}
// Move from general purpose register
// mov Vd.T[index], Rn
void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {

32
src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp

@ -3352,12 +3352,12 @@ void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
pmull2(v19, T8H, v0, v4, T16B);
pmull2(v17, T8H, v0, v6, T16B);
uzp1(v24, v20, v22, T8H);
uzp2(v25, v20, v22, T8H);
uzp1(v24, T8H, v20, v22);
uzp2(v25, T8H, v20, v22);
eor(v20, T16B, v24, v25);
uzp1(v26, v16, v18, T8H);
uzp2(v27, v16, v18, T8H);
uzp1(v26, T8H, v16, v18);
uzp2(v27, T8H, v16, v18);
eor(v16, T16B, v26, v27);
ushll2(v22, T4S, v20, T8H, 8);
@ -3371,8 +3371,8 @@ void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
eor(v20, T16B, v21, v20);
eor(v16, T16B, v17, v16);
uzp1(v17, v16, v20, T2D);
uzp2(v21, v16, v20, T2D);
uzp1(v17, T2D, v16, v20);
uzp2(v21, T2D, v16, v20);
eor(v17, T16B, v17, v21);
ushll2(v20, T2D, v17, T4S, 16);
@ -3381,8 +3381,8 @@ void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
eor(v20, T16B, v20, v22);
eor(v16, T16B, v16, v18);
uzp1(v17, v20, v16, T2D);
uzp2(v21, v20, v16, T2D);
uzp1(v17, T2D, v20, v16);
uzp2(v21, T2D, v20, v16);
eor(v28, T16B, v17, v21);
pmull(v22, T8H, v1, v5, T8B);
@ -3397,12 +3397,12 @@ void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
ld1(v0, v1, T2D, post(buf, 32));
uzp1(v24, v20, v22, T8H);
uzp2(v25, v20, v22, T8H);
uzp1(v24, T8H, v20, v22);
uzp2(v25, T8H, v20, v22);
eor(v20, T16B, v24, v25);
uzp1(v26, v16, v18, T8H);
uzp2(v27, v16, v18, T8H);
uzp1(v26, T8H, v16, v18);
uzp2(v27, T8H, v16, v18);
eor(v16, T16B, v26, v27);
ushll2(v22, T4S, v20, T8H, 8);
@ -3416,8 +3416,8 @@ void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
eor(v20, T16B, v21, v20);
eor(v16, T16B, v17, v16);
uzp1(v17, v16, v20, T2D);
uzp2(v21, v16, v20, T2D);
uzp1(v17, T2D, v16, v20);
uzp2(v21, T2D, v16, v20);
eor(v16, T16B, v17, v21);
ushll2(v20, T2D, v16, T4S, 16);
@ -3426,8 +3426,8 @@ void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
eor(v20, T16B, v22, v20);
eor(v16, T16B, v16, v18);
uzp1(v17, v20, v16, T2D);
uzp2(v21, v20, v16, T2D);
uzp1(v17, T2D, v20, v16);
uzp2(v21, T2D, v20, v16);
eor(v20, T16B, v17, v21);
shl(v16, T2D, v28, 1);