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8295069: [PPC64] Performance regression after JDK-8290025

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Reviewed-by: rrich, lucy
This commit is contained in:
Martin Doerr 2022-10-11 19:19:41 +00:00
parent d362e16924
commit 945950d863
5 changed files with 35 additions and 16 deletions
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16
src/hotspot/cpu/ppc/gc/shared/barrierSetAssembler_ppc.cpp
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@ -1,6 +1,6 @@
/*
* Copyright (c) 2018, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2018, 2021 SAP SE. All rights reserved.
* Copyright (c) 2018, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2018, 2022 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -23,7 +23,6 @@
*
*/
#include "nativeInst_ppc.hpp"
#include "precompiled.hpp"
#include "asm/macroAssembler.inline.hpp"
#include "classfile/classLoaderData.hpp"
@ -163,13 +162,18 @@ void BarrierSetAssembler::nmethod_entry_barrier(MacroAssembler* masm, Register t
// Actual patching is done in (platform-specific part of) BarrierSetNMethod.
__ load_const32(tmp, 0 /* Value is patched */); // 2 instructions
__ lwz(R0, in_bytes(bs_nm->thread_disarmed_offset()), R16_thread);
// Low order half of 64 bit value is currently used.
__ ld(R0, in_bytes(bs_nm->thread_disarmed_offset()), R16_thread);
__ cmpw(CCR0, R0, tmp);
__ bnectrl(CCR0);
// Oops may have been changed; exploiting isync semantics (used as acquire) to make those updates observable.
__ isync();
// Oops may have been changed. Make those updates observable.
// "isync" can serve both, data and instruction patching.
// But, many GCs don't modify nmethods during a concurrent phase.
if (nmethod_patching_type() != NMethodPatchingType::stw_instruction_and_data_patch) {
__ isync();
}
__ block_comment("} nmethod_entry_barrier (nmethod_entry_barrier)");
}

12
src/hotspot/cpu/ppc/gc/shared/barrierSetAssembler_ppc.hpp
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@ -1,6 +1,6 @@
/*
* Copyright (c) 2018, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2018, 2021 SAP SE. All rights reserved.
* Copyright (c) 2018, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2018, 2022 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -30,7 +30,11 @@
#include "memory/allocation.hpp"
#include "oops/access.hpp"
class InterpreterMacroAssembler;
enum class NMethodPatchingType {
stw_instruction_and_data_patch,
conc_instruction_and_data_patch,
conc_data_patch
};
class BarrierSetAssembler: public CHeapObj<mtGC> {
public:
@ -58,6 +62,8 @@ public:
virtual void barrier_stubs_init() {}
virtual NMethodPatchingType nmethod_patching_type() { return NMethodPatchingType::stw_instruction_and_data_patch; }
virtual void nmethod_entry_barrier(MacroAssembler* masm, Register tmp);
virtual void c2i_entry_barrier(MacroAssembler* masm, Register tmp1, Register tmp2, Register tmp3);
};

12
src/hotspot/cpu/ppc/gc/shared/barrierSetNMethod_ppc.cpp
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@ -26,6 +26,8 @@
#include "code/codeBlob.hpp"
#include "code/nmethod.hpp"
#include "code/nativeInst.hpp"
#include "gc/shared/barrierSet.hpp"
#include "gc/shared/barrierSetAssembler.hpp"
#include "gc/shared/barrierSetNMethod.hpp"
#include "utilities/debug.hpp"
@ -74,7 +76,7 @@ public:
get_patchable_instruction_handle()->verify();
current_instruction += 2;
verify_op_code(current_instruction, Assembler::LWZ_OPCODE);
verify_op_code(current_instruction, Assembler::LD_OPCODE);
// cmpw (mnemonic)
verify_op_code(current_instruction, Assembler::CMP_OPCODE);
@ -82,7 +84,7 @@ public:
// bnectrl (mnemonic) (weak check; not checking the exact type)
verify_op_code(current_instruction, Assembler::BCCTR_OPCODE);
verify_op_code(current_instruction, Assembler::ISYNC_OPCODE);
// isync is optional
}
private:
@ -100,7 +102,11 @@ private:
};
static NativeNMethodBarrier* get_nmethod_barrier(nmethod* nm) {
address barrier_address = nm->code_begin() + nm->frame_complete_offset() + (-9 * 4);
BarrierSetAssembler* bs_asm = BarrierSet::barrier_set()->barrier_set_assembler();
address barrier_address = nm->code_begin() + nm->frame_complete_offset() + (-8 * 4);
if (bs_asm->nmethod_patching_type() != NMethodPatchingType::stw_instruction_and_data_patch) {
barrier_address -= 4; // isync (see nmethod_entry_barrier)
}
auto barrier = reinterpret_cast<NativeNMethodBarrier*>(barrier_address);
debug_only(barrier->verify());

5
src/hotspot/cpu/ppc/gc/shenandoah/shenandoahBarrierSetAssembler_ppc.hpp
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@ -1,6 +1,6 @@
/*
* Copyright (c) 2018, 2021, Red Hat, Inc. All rights reserved.
* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
* Copyright (c) 2018, 2022, Red Hat, Inc. All rights reserved.
* Copyright (c) 2012, 2022 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -61,6 +61,7 @@ private:
void resolve_forward_pointer_not_null(MacroAssembler* masm, Register dst, Register tmp);
public:
virtual NMethodPatchingType nmethod_patching_type() { return NMethodPatchingType::conc_data_patch; }
/* ==== C1 stubs ==== */
#ifdef COMPILER1

6
src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.hpp
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@ -1,6 +1,6 @@
/*
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2021 SAP SE. All rights reserved.
* Copyright (c) 2021, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2021, 2022 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -64,6 +64,8 @@ public:
virtual void try_resolve_jobject_in_native(MacroAssembler* masm, Register dst, Register jni_env,
Register obj, Register tmp, Label& slowpath);
virtual NMethodPatchingType nmethod_patching_type() { return NMethodPatchingType::conc_data_patch; }
#ifdef COMPILER1
void generate_c1_load_barrier_test(LIR_Assembler* ce,
LIR_Opr ref) const;