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8236179: C1 register allocation error with T_ADDRESS

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Reviewed-by: rkennke, vlivanov, roland, mdoerr
This commit is contained in:
Aditya Mandaleeka 2019-12-20 19:51:00 +01:00 committed by Martin Doerr
parent 0591a66b90
commit 950ebec4a9
10 changed files with 25 additions and 7 deletions

2
src/hotspot/cpu/aarch64/c1_FrameMap_aarch64.cpp

@ -49,6 +49,8 @@ LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) {
opr = as_oop_opr(reg);
} else if (type == T_METADATA) {
opr = as_metadata_opr(reg);
} else if (type == T_ADDRESS) {
opr = as_address_opr(reg);
} else {
opr = as_opr(reg);
}

4
src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp

@ -759,7 +759,7 @@ void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool po
if (is_reference_type(type)) {
__ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
__ verify_oop(src->as_register());
} else if (type == T_METADATA || type == T_DOUBLE) {
} else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
__ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
} else {
__ strw(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
@ -872,7 +872,7 @@ void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
if (is_reference_type(type)) {
__ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
__ verify_oop(dest->as_register());
} else if (type == T_METADATA) {
} else if (type == T_METADATA || type == T_ADDRESS) {
__ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
} else {
__ ldrw(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));

4
src/hotspot/cpu/arm/c1_FrameMap_arm.cpp

@ -80,10 +80,12 @@ LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) {
Register reg = r_1->as_Register();
if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
opr = as_long_opr(reg, r_2->as_Register());
} else if (type == T_OBJECT || type == T_ARRAY) {
} else if (is_reference_type(type)) {
opr = as_oop_opr(reg);
} else if (type == T_METADATA) {
opr = as_metadata_opr(reg);
} else if (type == T_ADDRESS) {
opr = as_address_opr(reg);
} else {
// PreferInterpreterNativeStubs should ensure we never need to
// handle a long opr passed as R3+stack_slot

4
src/hotspot/cpu/ppc/c1_FrameMap_ppc.cpp

@ -54,6 +54,10 @@ LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) {
opr = as_long_opr(reg);
} else if (is_reference_type(type)) {
opr = as_oop_opr(reg);
} else if (type == T_METADATA) {
opr = as_metadata_opr(reg);
} else if (type == T_ADDRESS) {
opr = as_address_opr(reg);
} else {
opr = as_opr(reg);
}

2
src/hotspot/cpu/s390/c1_FrameMap_s390.cpp

@ -50,6 +50,8 @@ LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) {
opr = as_oop_opr(reg);
} else if (type == T_METADATA) {
opr = as_metadata_opr(reg);
} else if (type == T_ADDRESS) {
opr = as_address_opr(reg);
} else {
opr = as_opr(reg);
}

4
src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp

@ -1007,7 +1007,7 @@ void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
if (is_reference_type(type)) {
__ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
__ verify_oop(dest->as_register());
} else if (type == T_METADATA) {
} else if (type == T_METADATA || type == T_ADDRESS) {
__ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
} else {
__ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), false);
@ -1035,7 +1035,7 @@ void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool po
if (is_reference_type(type)) {
__ verify_oop(src->as_register());
__ reg2mem_opt(src->as_register(), dst, true);
} else if (type == T_METADATA) {
} else if (type == T_METADATA || type == T_ADDRESS) {
__ reg2mem_opt(src->as_register(), dst, true);
} else {
__ reg2mem_opt(src->as_register(), dst, false);

2
src/hotspot/cpu/sparc/c1_FrameMap_sparc.cpp

@ -55,6 +55,8 @@ LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) {
opr = as_oop_opr(reg);
} else if (type == T_METADATA) {
opr = as_metadata_opr(reg);
} else if (type == T_ADDRESS) {
opr = as_address_opr(reg);
} else {
opr = as_opr(reg);
}

2
src/hotspot/cpu/x86/c1_FrameMap_x86.cpp

@ -54,6 +54,8 @@ LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) {
opr = as_oop_opr(reg);
} else if (type == T_METADATA) {
opr = as_metadata_opr(reg);
} else if (type == T_ADDRESS) {
opr = as_address_opr(reg);
} else {
opr = as_opr(reg);
}

4
src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp

@ -935,7 +935,7 @@ void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool po
if (is_reference_type(type)) {
__ verify_oop(src->as_register());
__ movptr (dst, src->as_register());
} else if (type == T_METADATA) {
} else if (type == T_METADATA || type == T_ADDRESS) {
__ movptr (dst, src->as_register());
} else {
__ movl (dst, src->as_register());
@ -1116,7 +1116,7 @@ void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
if (is_reference_type(type)) {
__ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
__ verify_oop(dest->as_register());
} else if (type == T_METADATA) {
} else if (type == T_METADATA || type == T_ADDRESS) {
__ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
} else {
__ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));

4
src/hotspot/share/c1/c1_FrameMap.hpp

@ -185,6 +185,10 @@ class FrameMap : public CompilationResourceObj {
return LIR_OprFact::single_cpu_metadata(cpu_reg2rnr(r));
}
static LIR_Opr as_address_opr(Register r) {
return LIR_OprFact::single_cpu_address(cpu_reg2rnr(r));
}
FrameMap(ciMethod* method, int monitors, int reserved_argument_area_size);
bool finalize_frame(int nof_slots);