8322753: RISC-V: C2 ReverseBytesV
Reviewed-by: fyang
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@ -1887,8 +1887,9 @@ enum Nf {
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}
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// Vector Bit-manipulation used in Cryptography (Zvkb) Extension
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INSN(vbrev8_v, 0b1010111, 0b010, 0b01000, 0b010010);
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INSN(vrev8_v, 0b1010111, 0b010, 0b01001, 0b010010);
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INSN(vbrev_v, 0b1010111, 0b010, 0b01010, 0b010010); // reverse bits in every element
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INSN(vbrev8_v, 0b1010111, 0b010, 0b01000, 0b010010); // reverse bits in every byte of element
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INSN(vrev8_v, 0b1010111, 0b010, 0b01001, 0b010010); // reverse bytes in every elememt
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#undef INSN
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@ -73,6 +73,7 @@ source %{
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return false;
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}
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break;
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case Op_ReverseBytesV:
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case Op_PopCountVL:
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case Op_PopCountVI:
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return UseZvbb;
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@ -3756,6 +3757,32 @@ instruct vsignum_reg(vReg dst, vReg zero, vReg one, vRegMask_V0 v0) %{
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ins_pipe(pipe_slow);
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%}
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// -------------------------------- Reverse Bytes Vector Operations ------------------------
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instruct vreverse_bytes_masked(vReg dst, vReg src, vRegMask_V0 v0) %{
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match(Set dst (ReverseBytesV src v0));
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format %{ "vreverse_bytes_masked $dst, $src, v0" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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uint vlen = Matcher::vector_length(this);
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__ vsetvli_helper(bt, vlen);
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__ vrev8_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), Assembler::v0_t);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct vreverse_bytes(vReg dst, vReg src) %{
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match(Set dst (ReverseBytesV src));
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format %{ "vreverse_bytes $dst, $src" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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uint vlen = Matcher::vector_length(this);
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__ vsetvli_helper(bt, vlen);
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__ vrev8_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
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%}
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ins_pipe(pipe_slow);
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%}
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// ---------------- Convert Half Floating to Floating Vector Operations ----------------
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// half precision -> single
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@ -3790,7 +3817,7 @@ instruct vconvF2HF(vReg dst, vReg src, vReg vtmp, vRegMask_V0 v0, iRegINoSp tmp)
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// ------------------------------ Popcount vector ------------------------------
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instruct vpopcount_mask(vReg dst, vReg src, vRegMask_V0 v0) %{
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instruct vpopcount_masked(vReg dst, vReg src, vRegMask_V0 v0) %{
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match(Set dst (PopCountVI src v0));
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match(Set dst (PopCountVL src v0));
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ins_cost(VEC_COST);
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@ -42,7 +42,8 @@ import jdk.test.lib.Utils;
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* @library /test/lib /
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* @summary [vectorapi] REVERSE_BYTES for byte type should not emit any instructions
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* @requires vm.compiler2.enabled
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* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") | os.arch == "aarch64"
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* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") | os.arch == "aarch64" |
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* (os.arch == "riscv64" & vm.cpu.features ~= ".*zvbb.*")
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* @modules jdk.incubator.vector
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*
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* @run driver compiler.vectorapi.VectorReverseBytesTest
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@ -25,7 +25,8 @@
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* @bug 8288112
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* @summary Auto-vectorization of ReverseBytes operations.
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* @requires vm.compiler2.enabled
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* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") | os.simpleArch == "AArch64"
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* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") | os.simpleArch == "AArch64" |
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* (os.simpleArch == "riscv64" & vm.cpu.features ~= ".*zvbb.*")
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* @library /test/lib /
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* @run driver compiler.vectorization.TestReverseBytes
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*/
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@ -227,6 +227,9 @@ public class BasicCharOpTest extends VectorizationTestRunner {
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@Test
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@IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"},
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counts = {IRNode.REVERSE_BYTES_VS, ">0"})
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@IR(applyIfPlatform = {"riscv64", "true"},
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applyIfCPUFeature = {"zvbb", "true"},
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counts = {IRNode.REVERSE_BYTES_VS, ">0"})
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public char[] reverseBytesWithChar() {
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char[] res = new char[SIZE];
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for (int i = 0; i < SIZE; i++) {
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@ -250,6 +250,9 @@ public class BasicShortOpTest extends VectorizationTestRunner {
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@Test
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@IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"},
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counts = {IRNode.REVERSE_BYTES_VS, ">0"})
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@IR(applyIfPlatform = {"riscv64", "true"},
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applyIfCPUFeature = {"zvbb", "true"},
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counts = {IRNode.REVERSE_BYTES_VS, ">0"})
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public short[] reverseBytesWithShort() {
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short[] res = new short[SIZE];
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for (int i = 0; i < SIZE; i++) {
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