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8318953: RISC-V: Small refactoring for MacroAssembler::test_bit

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Reviewed-by: fyang, fjiang, luhenry
This commit is contained in:
Gui Cao 2023-10-30 00:31:08 +00:00 committed by Fei Yang
parent ce0ca47641
commit 988e1dfe6e
3 changed files with 10 additions and 4 deletions
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2
src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
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@ -63,7 +63,7 @@ void C2_MacroAssembler::fast_lock(Register objectReg, Register boxReg, Register
if (DiagnoseSyncOnValueBasedClasses != 0) {
load_klass(flag, oop);
lwu(flag, Address(flag, Klass::access_flags_offset()));
test_bit(flag, flag, exact_log2(JVM_ACC_IS_VALUE_BASED_CLASS), tmp /* tmp */);
test_bit(flag, flag, exact_log2(JVM_ACC_IS_VALUE_BASED_CLASS));
bnez(flag, cont, true /* is_far */);
}

10
src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
View File

@ -4677,13 +4677,19 @@ void MacroAssembler::rt_call(address dest, Register tmp) {
}
}
void MacroAssembler::test_bit(Register Rd, Register Rs, uint32_t bit_pos, Register tmp) {
void MacroAssembler::test_bit(Register Rd, Register Rs, uint32_t bit_pos) {
assert(bit_pos < 64, "invalid bit range");
if (UseZbs) {
bexti(Rd, Rs, bit_pos);
return;
}
andi(Rd, Rs, 1UL << bit_pos, tmp);
int64_t imm = (int64_t)(1UL << bit_pos);
if (is_simm12(imm)) {
and_imm12(Rd, Rs, imm);
} else {
srli(Rd, Rs, bit_pos);
and_imm12(Rd, Rd, 1);
}
}
// Implements lightweight-locking.

2
src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
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@ -1240,7 +1240,7 @@ public:
void shadd(Register Rd, Register Rs1, Register Rs2, Register tmp, int shamt);
// test single bit in Rs, result is set to Rd
void test_bit(Register Rd, Register Rs, uint32_t bit_pos, Register tmp = t0);
void test_bit(Register Rd, Register Rs, uint32_t bit_pos);
// Here the float instructions with safe deal with some exceptions.
// e.g. convert from NaN, +Inf, -Inf to int, float, double