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8171410: aarch64: long multiplyExact shifts by 31 instead of 63

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Reviewed-by: aph
This commit is contained in:
Ed Nevill 2016-12-18 17:26:44 -05:00
parent 4e860e58a3
commit 99ba5922e4
1 changed files with 4 additions and 4 deletions

8
hotspot/src/cpu/aarch64/vm/aarch64.ad

@ -14086,7 +14086,7 @@ instruct overflowMulL_reg(rFlagsReg cr, iRegL op1, iRegL op2)
format %{ "mul rscratch1, $op1, $op2\t#overflow check long\n\t"
"smulh rscratch2, $op1, $op2\n\t"
"cmp rscratch2, rscratch1, ASR #31\n\t"
"cmp rscratch2, rscratch1, ASR #63\n\t"
"movw rscratch1, #0x80000000\n\t"
"cselw rscratch1, rscratch1, zr, NE\n\t"
"cmpw rscratch1, #1" %}
@ -14094,7 +14094,7 @@ instruct overflowMulL_reg(rFlagsReg cr, iRegL op1, iRegL op2)
ins_encode %{
__ mul(rscratch1, $op1$$Register, $op2$$Register); // Result bits 0..63
__ smulh(rscratch2, $op1$$Register, $op2$$Register); // Result bits 64..127
__ cmp(rscratch2, rscratch1, Assembler::ASR, 31); // Top is pure sign ext
__ cmp(rscratch2, rscratch1, Assembler::ASR, 63); // Top is pure sign ext
__ movw(rscratch1, 0x80000000); // Develop 0 (EQ),
__ cselw(rscratch1, rscratch1, zr, Assembler::NE); // or 0x80000000 (NE)
__ cmpw(rscratch1, 1); // 0x80000000 - 1 => VS
@ -14112,7 +14112,7 @@ instruct overflowMulL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, rF
format %{ "mul rscratch1, $op1, $op2\t#overflow check long\n\t"
"smulh rscratch2, $op1, $op2\n\t"
"cmp rscratch2, rscratch1, ASR #31\n\t"
"cmp rscratch2, rscratch1, ASR #63\n\t"
"b$cmp $labl" %}
ins_cost(4 * INSN_COST); // Branch is rare so treat as INSN_COST
ins_encode %{
@ -14120,7 +14120,7 @@ instruct overflowMulL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, rF
Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
__ mul(rscratch1, $op1$$Register, $op2$$Register); // Result bits 0..63
__ smulh(rscratch2, $op1$$Register, $op2$$Register); // Result bits 64..127
__ cmp(rscratch2, rscratch1, Assembler::ASR, 31); // Top is pure sign ext
__ cmp(rscratch2, rscratch1, Assembler::ASR, 63); // Top is pure sign ext
__ br(cond == Assembler::VS ? Assembler::NE : Assembler::EQ, *L);
%}